Semiconductor device and electronic system including the same

Patent metadata

Field	Value
Publication number	US-12347778-B2
Application number	US-202217722672-A
Country	US
Kind code	B2
Filing date	Apr 18, 2022
Priority date	Aug 13, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including electrodes stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region;
vertical patterns penetrating the electrode structure;
a cell contact on the connection region and connected to the pad portion; and
an insulating pillar below the cell contact, with the pad portion interposed therebetween,
wherein the pad portion comprises,
a first portion having a top surface higher than the line portion, and
a second portion being between the cell contact and the insulating pillar, the second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar, and

wherein a thickness of the second portion is larger than a thickness of the first portion.

2. The semiconductor device of claim 1 , further comprising:
a contact insulating pattern on a side surface of the insulating pillar,
wherein the first protruding portion covers an inner side surface of the contact insulating pattern.

3. The semiconductor device of claim 2 , wherein a bottom surface of the first portion covers a top surface of the contact insulating pattern.

4. The semiconductor device of claim 2 , wherein
the pad portion further comprises a third portion, the third portion connected to the line portion and being below the first portion, and
the third portion covers an outer side surface of the contact insulating pattern.

5. The semiconductor device of claim 1 , wherein the electrode structure further comprises:
interlayer insulating layers between the electrodes; and
a horizontal insulating layer between the electrodes and the interlayer insulating layers,
wherein the horizontal insulating layer extends into a region between the insulating pillar and the first protruding portion of the second portion.

6. The semiconductor device of claim 1 , wherein the second portion further comprises a second protruding portion, which extends in a direction away from the substrate and is connected to the cell contact.

7. The semiconductor device of claim 6 , wherein the electrode structure further comprises:
interlayer insulating layers between the electrodes; and
a horizontal insulating layer between the electrodes and the interlayer insulating layers,
wherein the second protruding portion of the second portion penetrates the horizontal insulating layer and is connected to the cell contact.

8. The semiconductor device of claim 1 , wherein the top surface of the insulating pillar is higher than a bottom surface of the line portion to which a corresponding one of the electrodes is connected.

9. The semiconductor device of claim 8 , wherein
the first protruding portion comprises a recess region, and
the insulating pillar fills the recess region.

10. The semiconductor device of claim 8 , further comprising:
a contact insulating pattern on a side surface of the insulating pillar,
wherein the contact insulating pattern comprises a plurality of contact insulating patterns along the side surface of the insulating pillar, and
the insulating pillar penetrates at least one of the electrodes and is spaced apart from the at least one of the electrodes by the contact insulating pattern.

11. The semiconductor device of claim 1 , wherein
the semiconductor device comprises a first chip including the substrate and the electrode structure, and a second chip connected to the first chip and including a peripheral circuit region, and
the electrode structure and the cell contact are between the substrate of the first chip and the second chip.

12. The semiconductor device of claim 11 , wherein
the first chip further comprises a first bonding metal layer,
the second chip further comprises a second bonding metal layer, and
the first bonding metal layer and the second bonding metal layer are in direct contact with each other, at an interface between the first chip and the second chip.

13. A semiconductor device, comprising:
a substrate including a cell array region and a connection region;
an electrode structure including electrodes stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region;
vertical patterns penetrating the electrode structure;
a cell contact on the connection region and connected to the pad portion; and
an insulating pillar below the cell contact, with the pad portion interposed therebetween,
wherein the pad portion comprises,
a first portion having a top surface higher than the line portion, and
a second portion being between the cell contact and the insulating pillar, the second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar, and

wherein the insulating pillar is connected to the substrate.

14. A semiconductor device, comprising:
a first chip including a substrate, the substrate including a cell array region and a connection region; and
a second chip including a peripheral circuit region and a second bonding metal layer,
wherein the first chip comprises,
an electrode structure between the substrate and the second chip, the electrode structure comprising electrodes stacked on the substrate, each the electrodes including a line portion on the cell array region and a pad portion on the connection region;
vertical patterns penetrating the electrode structure;
a cell contact on the connection region and connected to the pad portion;
an insulating pillar below the cell contact, with the pad portion interposed therebetween;
a contact insulating pattern on a side surface of the insulating pillar; and
a first bonding metal layer on the cell contact,
wherein the pad portion comprises,
a first portion on a second portion and having a top surface higher than the line portion,
the second portion between the cell contact and the insulating pillar, and
a third portion connected to the line portion, and
wherein the first bonding metal layer and the second bonding metal layer are in direct contact with each other, at an interface between the first chip and the second chip.

15. The semiconductor device of claim 14 , wherein a thickness of the second portion is larger than a thickness of the first portion.

16. The semiconductor device of claim 14 , wherein the second portion comprises:
a first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar; and
a second protruding portion extending in a direction away from the substrate and connecting to the cell contact.

17. The semiconductor device of claim 16 , wherein the electrode structure further comprises:
interlayer insulating layers between the electrodes; and
a horizontal insulating layer between the electrodes and the interlayer insulating layers,
wherein the horizontal insulating layer extends into a region between the insulating pillar and the first protruding portion of the second portion.

18. The semiconductor device of claim 16 , wherein the first protruding portion covers an inner side surface of the contact insulating pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyunghwan
• Kim Yongseok
• Woo Dongsoo
• Lim Junhee

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title