Testing integrated circuit designs with accelerated replay

Patent metadata

Field	Value
Publication number	US-12346643-B1
Application number	US-202117301251-A
Country	US
Kind code	B1
Filing date	Mar 30, 2021
Priority date	Mar 30, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A technique to stress test an integrated circuit design under test in a simulation environment may include running a simulation that includes providing bus interface transactions and idle cycles on a bus interface of an integrated circuit design. The technique may further include capturing bus interface activity on the bus interface during the simulation to generate a stimulus file and replaying the simulation by executing a test bench driver that reads the stimulus file and injects the bus interface transactions with modified idle cycles onto the bus interface of the integrated circuit design.

First claim

What is claimed is:

1. A computer-implemented method for testing an integrated circuit design, the method comprising:
running a simulation that includes:
reading, by a controller model, controller instructions from a memory model;
executing, by the controller model, microcode to translate the controller instructions into device instructions for an integrated circuit design under test; and
dispatching, by the controller model, the device instructions onto a bus interface between the controller model and the integrated circuit design, wherein the device instructions are dispatched onto the bus interface with intervening idle cycles;

capturing bus interface activity on the bus interface to generate a stimulus file, wherein one or more of the intervening idle cycles are excluded from the stimulus file; and
executing a test bench driver to bypass the microcode and replay the simulation, wherein replaying the simulation includes:
reading, by the test bench driver, the stimulus file; and
injecting, by the test bench driver, the device instructions from the stimulus file into the integrated circuit design without the excluded one or more of the intervening idle cycles.

2. The computer-implemented method of claim 1 , wherein the bus interface includes:
a data bus;
a push signal to indicate that a valid device instruction is present on the data bus; and
a full signal generated by the integrated circuit design under test to indicate that a processing queue of the integrated circuit design is full.

3. The computer-implemented method of claim 2 , wherein in response to the integrated circuit design asserting the full signal, the test bench driver maintains a current device instruction on the data bus until the full signal is deasserted.

4. The computer-implemented method of claim 1 , wherein the controller model is held in reset while the test bench driver is injecting the device instructions.

5. A computer-implemented method, comprising:
running a simulation that includes providing bus interface transactions and idle cycles on a bus interface of an integrated circuit design under test;
capturing bus interface activity on the bus interface during the simulation to generate a stimulus file; and
replaying the simulation by executing a test bench driver that reads the stimulus file and injects the bus interface transactions with modified idle cycles onto the bus interface of the integrated circuit design under test.

6. The computer-implemented method of claim 5 , wherein the bus interface transactions include data movement instructions being dispatched to the integrated circuit design under test, the data movement instructions causing the integrated circuit design to fetch data from a memory model and load the data into a computational logic block of the integrated circuit design.

7. The computer-implemented method of claim 5 , wherein the bus interface transactions are generated by a controller model executing microcode.

8. The computer-implemented method of claim 7 , wherein the microcode executed by the controller model is a pre-release version that is undergoing optimization.

9. The computer-implemented method of claim 7 , wherein the controller model is held in reset while the simulation is being replayed.

10. The computer-implemented method of claim 5 , wherein the test bench driver is a system Verilog driver.

11. The computer-implemented method of claim 5 , wherein the stimulus file is a binary file or a text file.

12. The computer-implemented method of claim 5 , wherein the stimulus file includes data bus state information correlated with time information.

13. The computer-implemented method of claim 5 , wherein the stimulus file is generated by excluding a plurality of the idle cycles from the bus interface activity.

14. The computer-implemented method of claim 5 , wherein replaying the simulation includes removing a plurality of the idle cycles from the bus interface when the stimulus file is read.

15. The computer-implemented method of claim 5 , wherein the bus interface transactions are injected onto the bus interface with all of the idle cycles removed.

16. The computer-implemented method of claim 5 , wherein the bus interface includes a full signal indicating whether a processing queue of the integrated circuit design is full.

17. The computer-implemented method of claim 16 , wherein in response to the full signal being asserted, the test bench driver maintains a current bus interface transaction on the bus interface until the full signal is deasserted.

18. The computer-implemented method of claim 17 , wherein in response to the full signal being deasserted, the test bench driver injects a next bus interface transaction onto the bus interface.

19. The computer-implemented method of claim 5 , wherein the integrated circuit design is a hardware accelerator design.

20. A non-transitory computer readable medium storing code that, when executed by one or more processors, causes the one or more processors to implement a test bench driver that is configured to:
read a binary stimulus file containing bus interface activity captured in a prior simulation, the bus interface activity containing activity on a bus interface between a controller model and an integrated circuit design;
modify one or more idle cycles from the bus interface activity; and
inject the bus interface activity with the modified one or more idle cycles onto the bus interface while the controller model is being held in reset.

Assignees

• Amazon Tech Inc

Inventors

• Malkani Siddharth
• Lau Horace
• Amirineni Sundeep
• Vantrease Dana Michelle

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/331 Primary

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title