Testing integrated circuit designs with accelerated replay
US-12346643-B1 · Jul 1, 2025 · US
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Vantrease Dana Michelle patents
Vantrease Dana Michelle is listed as an inventor on 27 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Vantrease Dana Michelle |
| Total patents | 27 |
| First publication | Aug 1, 2019 |
| Latest publication | Jul 1, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Processing for multiple input data sets in a multi-layer neural network
US-12067492-B2 · Aug 20, 2024 · US
Reducing computations for data including padding
US-11960566-B1 · Apr 16, 2024 · US
Processing for multiple input data sets
US-2023351186-A1 · Nov 2, 2023 · US
Processing for multiple input data sets
US-11797853-B2 · Oct 24, 2023 · US
Performing concurrent operations in a processing element
US-2023325348-A1 · Oct 12, 2023 · US
Performing concurrent operations in a processing element
US-11720523-B2 · Aug 8, 2023 · US
Processing for multiple input data sets
US-2023014783-A1 · Jan 19, 2023 · US
Processing for multiple input data sets
US-11475306-B2 · Oct 18, 2022 · US
Scheduling neural network computations based on memory capacity
US-11461631-B2 · Oct 4, 2022 · US
Recent patents
Latest publications not already listed above.
Weight loading in an array
US-11275997-B1 · Mar 15, 2022 · US
Test generation of a distributed system
US-11275661-B1 · Mar 15, 2022 · US
Synchronization of concurrent computation engines
US-11175919-B1 · Nov 16, 2021 · US
Reducing computations for data including padding
US-10990650-B1 · Apr 27, 2021 · US
Accelerated quantized multiply-and-add operations
US-10983754-B2 · Apr 20, 2021 · US
Synchronization of concurrent computation engines
US-10922146-B1 · Feb 16, 2021 · US
Accelerated quantized multiply-and-add operations
US-2020293284-A1 · Sep 17, 2020 · US
Integrated circuit with rate limiting
US-10705985-B1 · Jul 7, 2020 · US
Accelerated quantized multiply-and-add operations
US-10678508-B2 · Jun 9, 2020 · US
Runtime augmentation of engine instructions
US-10664282-B1 · May 26, 2020 · US
Performing concurrent operations in a processing element
US-2020050582-A1 · Feb 13, 2020 · US
Performing concurrent operations in a processing element
US-10459876-B2 · Oct 29, 2019 · US
Scheduling network computations
US-2019294959-A1 · Sep 26, 2019 · US
Processing for multiple input data sets
US-2019294968-A1 · Sep 26, 2019 · US
Accelerated quantized multiply-and-add operations
US-2019294413-A1 · Sep 26, 2019 · US
Reducing traffic in hierarchical cache interconnects
US-10402329-B1 · Sep 3, 2019 · US
Performing concurrent operations in a processing element
US-2019236049-A1 · Aug 1, 2019 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Amazon Tech Inc | 27 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06N3/063 | 23 |
| G06N3/0464 | 22 |
| G06N3/045 | 22 |
| G06N3/08 | 16 |
| G06F17/15 | 9 |