Digital clock signal generator, chip, and method for generating spread-spectrum synchronous clock signals

Patent metadata

Field	Value
Publication number	US-12346148-B2
Application number	US-202318459053-A
Country	US
Kind code	B2
Filing date	Aug 31, 2023
Priority date	Oct 9, 2019
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A method for generating spread-spectrum synchronous clock signals includes comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback; generating a first control signal and a second control signal; determining an integer part I of a control word F to track the first frequency; registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0<r<1) of the control word F to provide a broadened boundary in frequency spectrum; and generating a synthesized periodic signal with the second frequency based on a base time unit Δ, the first frequency, and the control word F, the synthesized periodic signal being fed back as the feedback signal in the loop of feedback and outputted with the second frequency being locked within the broadened boundary.

First claim

What is claimed is:

1. A method for generating spread-spectrum synchronous clock signals comprising:
comparing an input signal of a first frequency with a feedback signal of a second frequency in a loop of feedback;
generating a first control signal and a second control signal;
determining an integer part I of a control word F to track the first frequency;
registering n levels for the first control signal and the second control signal to introduce n phase delays for randomly changing a fraction part r (0<r<1) of the control word F to provide a broadened boundary in frequency spectrum; and
generating a synthesized periodic signal with the second frequency based on a base time unit Δ, the first frequency, and the control word F, the synthesized periodic signal being fed back as the feedback signal in the loop of feedback and outputted with the second frequency being locked within the broadened boundary of the first frequency.

2. The method of claim 1 , further comprising generating K pulses of the first frequency with equally spaced phase shift of A, so that under control of the control word F (2≤F≤2K) the synthesized periodic signal is selected from one of the K pulses with an average period T=F·Δ and the second frequency, the second frequency being a time-average frequency equal to K/F multiplying the first frequency.

3. The method of claim 1 , further comprising:
detecting a relationship between the first frequency and the second frequency; and
generating a first control signal and a second control signal alternately in a first timeframe and a second timeframe one after another based on the relationship between the first frequency and the second frequency.

4. The method of claim 3 , further comprising:
determine whether the first frequency is greater or smaller than the second frequency; and
outputting either the first control signal in the first timeframe based on determination that the first frequency is greater than the second frequency or the second control signal in the second timeframe based on determination that the first frequency is smaller than the second frequency.

5. The method of claim 4 , wherein the first control signal is to control reducing the control word F in the first timeframe and the second control signal is to control increasing the control word F in the second timeframe, so that the control word F is switched between I and I+1 as the loop of feedback reaches a dynamic equilibrium with one first timeframe and one second timeframe appearing alternately one after another.

6. The method of claim 5 , wherein the dynamic equilibrium comprises one first timeframe and one second timeframe appearing alternately one after another on average, based on a number N A of output pulses having a first period T A =I·Δ in the first timeframe and a number N B of output pulses having a second period T B =(I+1)·Δ in the second timeframe, yielding a fraction number r to be a ratio of N B over a sum of N A and N B .

7. The method of claim 6 , further comprising:
receiving the first control signal to generate total n levels of first register-delayed control signals, or receiving the second control signal to generate total n levels of second register-delayed control signals;
randomly select a value of the fraction number r;
selecting any path associated with the n levels of the first register-delayed control signals and the n levels of the second register-delayed control signals; and
receiving the value of the fraction number r to determine the control word F.

8. The method of claim 7 , further comprising:
forming a first group of D-type flip-flops having n stages connected in series to receive the first control signal at the first one of the n stages of the first group of D-type flip-flops and to receive the feedback signal at each of the n stages of the first group of D-type flip-flops;
generating n levels of first register-delayed control signals;
forming a second group of D-type flip-flops having n stages connected in series to receive the second control signal at the first one of the n stages of the second group of D-type flip-flops and to receive the feedback signal at each of the n stages of the second group of D-type flip-flops; and
generating n levels of second register-delayed control signals.

9. The method of claim 8 , further comprising introducing n choices of N A and n choices of N B , and a randomly selected r=N B /(N A +N B ) to provide the broadened boundary defined by a maximum value of the feedback signal leading the input signal in phase as N A ·(T−T A ) and a maximum value of the feedback signal lagging behind the input signal in phase as N B ·(T B −T).

10. The method of claim 2 , further comprising using a first K-to-1 multiplexer coupled to an accumulation-register controlled by the control word F via an accumulator in a first path to input K pulses of the first frequency with equally spaced phase delay Δ, generating a low level of the synthesized periodic signal, using a second K-to-1 multiplexer coupled to an adder-register controlled by the half control word F/2 via an adder in a second path to input the K pulses of the first frequency with equally spaced phase delay Δ, generating a high level of the synthesized periodic signal, using a 2-to-1 multiplexer to interlock the first path and the second path to output either the high level or the low level of the synthesized periodic signal.

11. The method of claim 10 , further comprising transmitting the synthesized periodic signal as a spread-spectrum clock signal as the second frequency is substantially synchronous to the first frequency under a condition that a data-reception establishing time is less than half the period T minus a maximum value of the synthesized periodic signal leading the input signal in phase and a data-reception maintaining time is less than half the period T minus a maximum value of the synthesized periodic signal lagging behind the input signal in phase.

12. The method of claim 10 , further comprising toggling transition of a upper path and a lower path.

13. The method of claim 1 , further comprising:
generating multiple pulses of the first frequency with equally spaced phase delay Δ;
obtaining a synthesized periodic signal with a time-average frequency from one of the multiple pulses controlled by a control word F, the synthesized periodic signal being used as a feedback signal;
comparing the input signal of the first frequency with the feedback signal of a second frequency in a loop of feedback; and
generating a first control signal and a second control signal alternately in a first timeframe and a second timeframe one after another based on relationship between the first frequency and the second frequency.

14. The method of claim 13 , further comprising updating an integer part I of the control word F based on the first control signal or the second control signal to allow the second frequency to track the first frequency.

15. The method of claim 14 , wherein updating an integer part I of the control word F comprises reducing the integer part I triggered by the first control signal in the first timeframe and increasing the integer part I triggered by the second control signal in the second timeframe.

16. The method of claim 13 , further comprising generating multiple delays in respective first control signal and the second control signal.

17. The method of claim 13 , further comprising selecting a fraction number r of the control word F randomly based on the multiple delays to provide a broadened phase boundary of a spread spectrum.

1

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Xiu Liming

Classifications

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title