Edge Generator-Based Phase Locked Loop Reference Clock Generator for Automated Test System

Patent metadata

Field	Value
Publication number	US-2016006441-A1
Application number	US-201414322375-A
Country	US
Kind code	A1
Filing date	Jul 2, 2014
Priority date	Jul 2, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a delay input. The edge generator may produce at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted. The phase locked loop may comprise a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency. The delay adjustment circuit may comprise an accumulator that may increase in value by a programmed amount for each cycle of the clock.

First claim

What is claimed is:

1 . A periodic signal generation circuit for generating a periodic signal of a programmable frequency, the periodic signal generation circuit comprising:
a phase locked loop, the phase locked loop comprising:
a controllable oscillator comprising a controllable oscillator output and a control input, the controllable oscillator being configured to produce the periodic signal at the controllable oscillator output with a frequency controlled by a control signal at the control input; and
a comparator comprising a first input and a second input and a comparator output, the comparator being configured to produce a signal at the comparator output, wherein the signal is representative of a difference in a phase characteristic between a first signal at the first input and a second signal at the second input, wherein the comparator output is coupled to the control input of the controllable oscillator, and wherein the controllable oscillator output is coupled to the second comparator input;
a programmable delay pulse generator circuit comprising a delay control input and an output, the output of the programmable delay pulse generator circuit being coupled to the first input of the comparator, the programmable delay pulse generator circuit being configured to output a pulse at the output of the programmable delay pulse generator circuit with a programmable delay following a transition of a reference signal; and an adjustment circuit to compute a value of the programmable delay for each of a plurality of cycles of the first signal.

2 . The periodic signal generation circuit of claim 1 , wherein:
the programmable delay pulse generator circuit further comprises an edge generation circuit of an automatic test system.

3 . The periodic signal generation circuit of claim 1 , wherein:
the phase locked loop is a divide-by-N phase locked loop.

4 . The periodic signal generation circuit of claim 3 , wherein:
the divide-by-N phase locked loop is an integer divide-by-N phase locked loop.

5 . The periodic signal generation circuit of claim 3 , wherein:
the divide-by-N phase locked loop is a fractional divide-by-N phase locked loop.

6 . The periodic signal generation circuit of claim 3 , wherein:
the phase locked loop is a divide-by-N phase locked loop that generates the second signal having a frequency that is 1/N of the frequency of the periodic signal; and the adjustment circuit computes the value of the delay for each period of the first signal.

7 . The periodic signal generation circuit of claim 1 , wherein:
the periodic signal generation circuit comprises a portion of a channel of an automated test system comprising a plurality of programmable edge generation circuits; and the programmable delay pulse generator circuit comprises a programmable edge generation circuit of the plurality of programmable edge generation circuits.

8 . The periodic signal generation circuit of claim 7 , wherein:
the reference signal comprises a period clock for the automated test system.

9 . The periodic signal generation circuit of claim 1 , wherein:
the adjustment circuit comprises a delta-sigma modulation circuit, the delta-sigma modulation circuit comprising an output coupled to the delay control input of the programmable delay pulse generator circuit.

10 . The periodic signal generation circuit of claim 1 , wherein:
the programmable delay pulse generator circuit further comprises:
at least one additional programmable delay pulse generator circuit; and
an averaging circuit coupled to:
the output of the programmable delay pulse generator circuit, an output of the at least one additional programmable delay pulse generator circuit, and the first input of the comparator.

11 . A method of generating a periodic signal of a programmed frequency, the method comprising:
generating an output signal comprising a controlled frequency that is controlled in response to a frequency control signal; producing a feedback signal by dividing in frequency the output signal; producing a reference signal; and comparing the feedback signal to the reference signal to generate the frequency control signal, wherein producing the reference signal comprises controlling a timing of each of a plurality of pulses in the reference signal such that the controlled frequency of the output signal corresponds to the programmed frequency.

12 . The method of claim 11 , wherein:
producing the reference signal further comprises, for each of a plurality of cycles of the reference signal, computing the delay in the reference signal by adding a delay adjustment to a computed delay in a prior cycle.

13 . The method of claim 12 , wherein:
the adding is performed using modular arithmetic.

14 . The method of claim 12 , wherein:
producing the reference signal further comprises generating a pulse in the reference signal at a time relative to an edge in a periodic timing signal, wherein the time is determined based on the computed delay for a respective cycle.

15 . The method of claim 11 , wherein:
producing the feedback signal comprises, for each of a plurality of cycles of the feedback signal, computing the delay in the feedback signal by adding a delay adjustment to a computed delay in a prior cycle.

16 . An automatic test system configured for generating a periodic signal of a programmable frequency, the automatic test system comprising:
a clock having a period; an edge generator coupled to the clock, the edge generator comprising an edge generator output, an enable input and a delay input, wherein the edge generator produces at the edge generator output a signal with a delay relative to an edge of the clock specified by a value at the delay input in each cycle of the clock for which the enable input is asserted; a phase locked loop comprising a reference input and a phase locked loop output configured to provide the periodic signal of the programmable frequency, wherein the reference input is coupled to the edge generator output; and a delay adjustment circuit comprising:
a delay adjustment circuit output coupled to the delay input of the edge generator, and
an accumulator that increases in value by a programmed amount for each cycle of the clock,
wherein, when the accumulated value exceeds the period of the clock, the delay adjustment circuit suppresses an enable signal coupled to the enable input of the edge generator and rolls over the accumulated value.

17 . The automatic test system of claim 16 , wherein:
the phase locked loop is a divide-by-N phase locked loop.

18 . The automatic test system of claim 17 , wherein:
the divide-by-N phase locked loop is an integer divide-by-N phase locked loop.

19 . The automatic test system of claim 17 , wherein:
the divide-by-N phase locked loop is a fractional divide-by-N phase locked loop.

20 . The automatic test system of claim 17 , wherein:
the divide-by-N phase locked loop generates a feedback signal having a frequency that is 1/N of the frequency of the phase locked loop output; and the delay adjustment circuit computes the value of the delay for each period of the reference signal.

21 . The automatic test system of claim 16 , further comprising:
at least one additional edge generator coupled to the clock; and an averaging circuit coupled to:
the edge generator output, an output of the at least one additional edge generator, and the reference input of the phase locked loop.

Assignees

• Teradyne Inc

Inventors

• Van Der Wagt Jan Paul Anthonie
• Sanders Jeffrey Wade
• Repucci Thomas Aquinas
• Sartschev Ronald A

Classifications

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03L7/0802 Primary

  the loop being adapted for reducing power consumption (H03L7/14 takes precedence) · CPC title