Turn-off power semiconductor device with gate runners

Patent metadata

Field	Value
Publication number	US-12342559-B2
Application number	US-202117914012-A
Country	US
Kind code	B2
Filing date	Mar 31, 2021
Priority date	Mar 31, 2020
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A turn-off power semiconductor device includes first and second thyristor cells, a common gate contact and a plurality of stripe-shaped electrically conductive first gate runners. Each first gate runner has a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion. The first end portion is directly connected to the common gate contact. The first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer. The second gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer. The first gate electrode layer is directly connected to the common gate contact. At least the first connecting portion of each first gate runner is separated from the first gate electrode layer.

First claim

The invention claimed is:

1. A turn-off power semiconductor device comprising:
a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a plurality of thyristor cells;
a common gate contact arranged on the first main side; and
a plurality of stripe-shaped electrically conductive first gate runners, each first gate runner having a first end portion, a second end portion opposite to the first end portion and a first connecting portion connecting the first end portion and the second end portion, wherein the first end portion is directly connected to the common gate contact and a longitudinal main axis of each first gate runner extends in a lateral direction away from the common gate contact;
wherein each thyristor cell comprises in an order from the first main side to the second main side:
a first emitter layer portion of a first conductivity type;
a first base layer portion of a second conductivity type different from the first conductivity type, the first emitter layer portion being in direct contact with the first base layer portion to form a first p-n junction between the first base layer portion and the first emitter layer portion;
a second base layer portion of the first conductivity type, wherein the first base layer portion is in direct contact with the second base layer portion to form a second p-n junction between the first base layer portion and the second base layer portion; and
a second emitter layer portion of the second conductivity type separated from the first base layer portion by the second base layer portion, wherein the second base layer portion is in direct contact with the second emitter layer portion to form a third p-n junction between the second base layer portion and the second emitter layer portion,
a first gate electrode layer portion arranged lateral to the first emitter layer portion, the first gate electrode layer portion forming an ohmic contact with the first base layer portion;
a first main electrode layer portion arranged on the first main side and forming an ohmic contact with the first emitter layer portion; and
a second main electrode layer portion arranged on the second main side and forming an ohmic contact with the second emitter layer portion;

wherein the plurality of thyristor cells comprises a plurality of first thyristor cells and a plurality of second thyristor cells;
wherein the first emitter layer portion of each first thyristor cell has a distance from the common gate contact that is smaller than a predetermined distance and the first emitter layer portion of each second thyristor cell has a distance from the common gate contact that is larger than the predetermined distance;
wherein the first gate electrode layer portions of all first thyristor cells are implemented as a first gate electrode layer laterally surrounding the first main electrode layer portions of all first thyristor cells;
wherein the first gate electrode layer portions of all second thyristor cells are implemented as a second gate electrode layer;
wherein the first gate electrode layer is directly connected to the common gate contact such that the first gate electrode layer portion of each first thyristor cell is electrically connected to the common gate contact;
wherein the second end portion of each first gate runner is directly connected to the second gate electrode layer;
wherein the common gate contact is ring-shaped in an orthogonal projection onto a plane parallel to the second main side and the longitudinal main axis of each first gate runner extends in a radial direction from the common gate contact towards a lateral center of the semiconductor wafer;
wherein, in the orthogonal projection onto the plane parallel to the second main side, a first ring-shaped gate electrode layer portion of the second gate electrode layer is arranged inside the ring-shaped common gate contact to laterally surround a remaining portion of the second gate electrode layer, wherein each first gate runner connects the common gate contact with the first ring-shaped electrode layer portion;
wherein at least the first connecting portion of each first gate runner is separated from the first gate electrode layer, so that any electrically conducting path from the first connecting portion of the each first gate runner to the first gate electrode layer passes at least through one of the first end portion of a same first gate runner, a second end portion of the same first gate runner and the semiconductor wafer; and
wherein an outer circumferential edge of the first ring-shaped gate electrode layer portion is separated from the first gate electrode layer so that any electrically conducting path from the second gate electrode layer passes at least through the semiconductor wafer or through one of the plurality of first gate runners.

2. The turn-off power semiconductor device according to claim 1 , wherein the first gate electrode layer, the second gate electrode layer, the common gate contact and the plurality of first gate runners each comprise a metal material.

3. The turn-off power semiconductor device according to claim 1 , wherein, in the orthogonal projection onto the plane parallel to the second main side, the semiconductor wafer has a circular shape, the first emitter layer portions of the plurality of thyristor cells are stripe-shaped and are arranged in concentric rings with a longitudinal main axis of the stripe-shaped first emitter layer portions respectively extending along a radial direction extending from the lateral center of the semiconductor wafer, wherein in each ring all first emitter layer portions have a same distance from the common gate contact.

4. The turn-off power semiconductor device according to claim 3 , wherein, in an innermost ring of first thyristor cells, a length of the first emitter layer portions varies as a function of a distance to next first gate runner, such that any first emitter layer portion adjacent to any one of the plurality of first gate runners has a shorter length than all other first emitter portions in the innermost ring that are not adjacent to one of the plurality of first gate runners.

5. The turn-off power semiconductor device according to claim 1 , wherein a length of each first gate runner in a radial direction is at least two times a maximal length of the first emitter layer portions of any first thyristor cell.

6. The turn-off power semiconductor device according to claim 5 , wherein the length of each first gate runner in the radial direction is at least three times the maximal length of the first emitter layer portions of any first thyristor cell.

7. The turn-off power semiconductor device according to claim 5 , wherein in the innermost ring of first thyristor cells the length of the first emitter layer portions increases with increasing distance from next first gate runner such that a distance of the first emitter layer portions in the innermost ring to the respective next first emitter layer portion of a second thyristor cell increases with increasing distance to the next first gate runner.

8. The turn-off power semiconductor device according to claim 1 , wherein a thickness of each first gate runner in a direction perpendicular to the lateral direction is at least 25% greater than a thickness of the first gate electrode layer at a position in a middle between two adjacent first emitter layer portions, wherein a thickness direction is a direction perpendicular to the second main side.

9. The turn-off power semiconductor device according to claim 8 , wherein the thickness of each first gate runner in a direction perpendicular to the lateral direction is at least 50% greater than the thickness of the first gate electrode layer at th

Assignees

• Hitachi Energy Ltd

Inventors

• Wikstroem Tobias
• Stiasny Thomas
• Commin Paul

Classifications

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D84/136

  in anti-parallel configurations, e.g. reverse current thyristor [RCT] · CPC title

• H10D64/291

  Gate electrodes for thyristors · CPC title

• H10D18/65 Primary

  with turn-off by field effect · CPC title

• H10D18/60 Primary

  Gate-turn-off devices · CPC title