Semiconductor device and method for controlling the same

Patent metadata

Field	Value
Publication number	US-12341503-B2
Application number	US-202318343435-A
Country	US
Kind code	B2
Filing date	Jun 28, 2023
Priority date	Sep 27, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

Provided is a semiconductor device that is easily controlled. The semiconductor device includes a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential, wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region, the transistor region includes a first gate controlled by a first gate signal, and the diode region includes a diode gate controlled by a diode gate signal.

First claim

What is claimed is:

1. A method for controlling a semiconductor device, the semiconductor device comprising:
a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential,
wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region,
the transistor region includes a first gate controlled by a first gate signal, and
the diode region includes a diode gate controlled by a diode gate signal,
the method comprising:
applying a positive voltage to the diode gate in the diode region in the second switching device as the diode gate signal to turn ON the diode gate, with a second timing earlier than a first timing at which a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region; and
setting the diode gate signal to a negative voltage or a zero voltage with the first timing or a timing earlier than the first timing to turn OFF the diode gate in the diode region in the second switching device,
wherein the second timing is earlier than the first timing by 20 microseconds at a maximum.

2. A method for controlling a semiconductor device, the semiconductor device comprising:
a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential,
wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region,
the transistor region includes a first gate controlled by a first gate signal, and a second gate controlled by a second gate signal,
the transistor region is disposed between a first main electrode and a second main electrode that are electrically separated from each other,
the first gate signal is a signal with respect to the first potential of the first main electrode, and
the second gate signal is a signal with respect to the second potential of the second main electrode,
the method comprising:
applying a positive voltage to the second gate as the second gate signal to turn ON the second gate, with a second timing earlier than a first timing at which a negative voltage or a zero voltage is applied to the first gate as the first gate signal to turn OFF the transistor region; and
setting the second gate signal to the negative voltage or the zero voltage to turn OFF the second gate between the first timing and a third timing at which a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region.

3. The method according to claim 2 ,
wherein the second timing is earlier than the first timing by 20 microseconds at a maximum.

4. A method for controlling a semiconductor device, the semiconductor device comprising:
a first switching device and a second switching device that are connected in series between a first potential and a second potential lower than the first potential,
wherein each of the first and second switching devices includes a transistor region, and a diode region electrically connected in anti-parallel to the transistor region,
the transistor region includes a first gate controlled by a first gate signal, and a second gate controlled by a second gate signal,
the diode region includes a diode gate controlled by a diode gate signal,
the transistor region is disposed between a first main electrode and a second main electrode that are electrically separated from each other,
the first gate signal is a signal with respect to the first potential of the first main electrode, and
the second gate signal is a signal with respect to the second potential of the second main electrode,
the method comprising:
applying a positive voltage to the second gate in the first switching device as the second gate signal to turn ON the second gate, with a second timing earlier than a first timing at which a negative voltage or a zero voltage is applied to the first gate as the first gate signal to turn OFF the transistor region;
setting the second gate signal to the negative voltage or the zero voltage to turn OFF the second gate between the first timing and a third timing at which a positive voltage is applied to the first gate in the first switching device as the first gate signal to turn ON the transistor region;
applying a positive voltage to the diode gate in the diode region in the second switching device as the diode gate signal to turn ON the diode gate with a fourth timing earlier than the third timing at which the transistor region is turned ON; and
setting the diode gate signal to the negative voltage or the zero voltage with the third timing or a timing earlier than the third timing to turn OFF the diode gate in the diode region in the second switching device.

5. The method according to claim 4 ,
wherein the second timing is earlier than the first timing by 20 microseconds at a maximum.

6. The method according to claim 4 ,
wherein the fourth timing is earlier than the third timing by 20 microseconds at a maximum.

Assignees

• Mitsubishi Electric Corp

Inventors

• Tsukuda Masanori
• Soneda Shinya
• Nishi Koichi

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H03K17/168 Primary

  in composite switches · CPC title