Semiconductor device and power conversion device

Patent metadata

Field	Value
Publication number	US-11282937-B2
Application number	US-201916976393-A
Country	US
Kind code	B2
Filing date	Feb 1, 2019
Priority date	Feb 28, 2018
Publication date	Mar 22, 2022
Grant date	Mar 22, 2022

Abstract

The invention provides an inexpensive flywheel diode having a low power loss. A semiconductor substrate side of a gate electrode provided on a surface of an anode electrode side of a semiconductor substrate including silicon is surrounded by a p layer, an n layer, and a p layer via a gate insulating film. The anode electrode is in contact with the p layer with a low resistance, and is also in contact with the n layer or the p layer, and a Schottky diode is formed between the anode electrode and the n layer or the p layer.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having a pair of surfaces;
a first semiconductor layer of a first conductivity type exposed on one surface of the semiconductor substrate;
a second semiconductor layer of the first conductivity type that is provided on the other surface side of the semiconductor substrate, in contact with the first semiconductor layer, and has a lower impurity concentration than that of the first semiconductor layer;
a third semiconductor layer of a second conductivity type formed in the second semiconductor layer and having a higher impurity concentration than that of the second semiconductor layer;
a fourth semiconductor layer of the first conductivity type formed in the third semiconductor layer;
a fifth semiconductor layer of the second conductivity type formed in the fourth semiconductor layer;
a cathode electrode provided on the one surface side of the semiconductor substrate and in ohmic contact with the first semiconductor layer;
an anode electrode provided on the other surface of the semiconductor substrate and in contact with the fifth semiconductor layer and the fourth semiconductor layer;
a gate electrode provided on the other surface of the semiconductor substrate; and
a gate insulating film formed between the gate electrode and the semiconductor substrate, wherein
a surface where the gate electrode is in contact with the semiconductor substrate via the gate insulating film is surrounded by the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, and a MOSFET is formed by the gate electrode, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, and
the anode electrode is in electrical contact with at least a portion of the fifth semiconductor layer at a low resistance, and includes, in a path connecting the anode electrode and the third semiconductor layer, a junction having a reverse blocking characteristic when the anode electrode is applied with a voltage with which the third semiconductor layer has a negative potential with respect to a potential of the anode electrode.

2. The semiconductor device according to claim 1 , wherein
the anode electrode is further in contact with the third semiconductor layer.

3. The semiconductor device according to claim 1 , wherein
a junction between the anode electrode and the fourth semiconductor layer is a Schottky junction.

4. The semiconductor device according to claim 2 , wherein
a junction between the anode electrode and the third semiconductor layer is a Schottky junction.

5. The semiconductor device according to claim 3 , wherein
the semiconductor substrate is made of a silicon semiconductor, and the Schottky junction has a barrier height of 0.4 eV to 0.7 eV.

6. The semiconductor device according to claim 1 , wherein
at least a region of the anode electrode in contact with the fourth semiconductor layer is formed of Ti or a Ti silicide.

7. The semiconductor device according to claim 2 , wherein
at least a region of the anode electrode in contact with the third semiconductor layer is formed of Ti or a Ti silicide.

8. The semiconductor device according to claim 1 , wherein
the impurity concentration of the third semiconductor layer and an impurity concentration of the fourth semiconductor layer are both 5×10 17 cm −3 or less.

9. The semiconductor device according to claim 1 , further comprising:
basic cells each including one or two of the gate electrodes and repeatedly arranged on the semiconductor substrate, wherein
in a case a point X is a position on the surface of the semiconductor substrate where the gate electrode is in contact with the fifth semiconductor layer via the gate insulating film, and where the anode electrode includes a region in contact with the fifth semiconductor layer between the point X and a second point X adjacent to the point X on one side, and when A is an interval between the point X and the second point X, and B is an interval between the point X and a third point X adjacent to the point X on an opposite side to the second point X, B>A is established.

10. The semiconductor device according to claim 1 , wherein
the gate electrode has any structure among a planar structure provided on the other surface of the semiconductor substrate, a trench gate structure dug in the semiconductor substrate from the other surface of the semiconductor substrate, and a side gate structure provided on a side surface of the semiconductor substrate.

11. The semiconductor device according to claim 1 , wherein
the MOSFET is configured to, after the MOSFET is turned off and the MOSFET becomes nonconductive from a state where the MOSFET is turned on and the anode electrode and the cathode electrode are forward-biased to be conductive, be turned on again when the anode electrode and the cathode electrode are backward-biased and a current starts flowing in a reverse direction between the anode electrode and the cathode electrode.

12. A power conversion device, comprising:
a pair of DC terminals;
a DC-AC conversion circuit configured by connecting two IGBT elements configured to turn on and off a current in series between the DC terminals; and
an AC terminal connected to a part where the two IGBT elements of the DC-AC conversion circuit are connected to each other, wherein
a MOS control diode including the semiconductor device according to claim 1 is connected in antiparallel with each of the IGBT elements.

13. The power conversion device according to claim 12 , wherein
the IGBT elements are each formed on the same semiconductor substrate as that of a semiconductor device wherein the semiconductor device comprises:
a semiconductor substrate having a pair of surfaces;
a first semiconductor layer of a first conductivity type exposed on one surface of the semiconductor substrate;
a second semiconductor layer of the first conductivity type that is provided on the other surface side of the semiconductor substrate, in contact with the first semiconductor layer, and has a lower impurity concentration than that of the first semiconductor layer;
a third semiconductor layer of a second conductivity type formed in the second semiconductor layer and having a higher impurity concentration than that of the second semiconductor layer;
a fourth semiconductor layer of the first conductivity type formed in the third semiconductor layer;
a fifth semiconductor layer of the second conductivity type formed in the fourth semiconductor layer;
a cathode electrode provided on the one surface side of the semiconductor substrate and in ohmic contact with the first semiconductor layer;
an anode electrode provided on the other surface of the semiconductor substrate and in contact with the fifth semiconductor layer and the fourth semiconductor layer;
a gate electrode provided on the other surface of the semiconductor substrate; and
a gate insulating film formed between the gate electrode and the semiconductor substrate, wherein
a surface where the gate electrode is in contact with the semiconductor substrate via the gate insulating film is surrounded by the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, and a MOSFET is formed by the gate electrode, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer, and
the anode electrode is in electrical contact with at least a portion of the fifth semiconductor layer at a low resistance, and includes, in a path connecting the anode electrode and the third semiconductor layer, a junction ha

Assignees

• Hitachi Power Semiconductor Device Ltd

Inventors

• Mori Mutsuhiro
• Miyoshi Tomoyuki
• Furukawa Tomoyasu
• Shiraishi Masaki

Classifications

• H10D12/211

  Gated diodes · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D8/50

  PIN diodes · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D12/461

  having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions · CPC title