Low stress films for advanced semiconductor applications

Patent metadata

Field	Value
Publication number	US-12341002-B2
Application number	US-202017310132-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jan 31, 2019
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

Films that can be useful in large area gap fill applications, such as in the formation of advanced 3D NAND devices, involve processing a semiconductor substrate by depositing on a patterned semiconductor substrate a doped silicon oxide film, the film having a thickness of at least 5 μm, and annealing the doped silicon oxide film to a temperature above the film glass transition temperature. In some embodiments, reflow of the film may occur. The composition and processing conditions of the doped silicon oxide film may be tailored so that the film exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal.

First claim

What is claimed is:

1. A method of processing a semiconductor substrate, the method comprising:
providing a patterned semiconductor substrate;
depositing on the patterned semiconductor substrate a doped silicon oxide film, wherein the doped silicon oxide film has a thickness of at least 5 μm; and
annealing the doped silicon oxide film to a temperature above the film glass transition temperature,
wherein the doped silicon oxide film is deposited by a chemical vapor deposition (CVD) process using precursors for silicon oxide and a dopant selected from the group consisting of B, P, and Ge, and
wherein each of the precursors for the dopant is selected from the group consisting of triethylborate (TEB), triethylphosphate (TEPO), and an organogermanium compound.

2. The method of claim 1 , wherein the silicon oxide precursor is tetraethyl orthosilicate (TEOS).

3. The method of claim 1 , wherein the CVD is a plasma enhanced CVD (PECVD) process.

4. The method of claim 1 , further comprising depositing an undoped silicon oxide capping layer on the doped silicon oxide film.

5. The method of claim 1 , wherein the doped silicon oxide film has a dopant concentration in the range of up to about 10 wt % of the film; or 0.5 to 10%; or 2-5%; or 2.5-3.5%.

6. The method of claim 5 , wherein the doped silicon oxide film has a dopant concentration in the range of about 0 to 10 wt % of the film B, 0 to 10% P, 0 to 10% Ge.

7. The method of claim 1 , wherein the patterned semiconductor substrate is a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a staircase pattern, and the doped silicon oxide film is deposited over the staircase pattern.

8. The method of claim 1 , wherein the doped silicon oxide film has a thickness of at least 10 μm.

9. The method of claim 1 , wherein the doped silicon oxide film is deposited at a thickness up to 20 μm by a single-pass deposition.

10. The method of claim 1 , wherein the doped silicon oxide film is deposited at a rate of at least 1 μm per minute.

11. The method of claim 1 , wherein the annealing of the doped silicon oxide film causes reflow of the film to occur.

12. A semiconductor device, comprising:
a 3D NAND structure having alternating oxide and nitride or polysilicon layers in a staircase pattern; and
a doped silicon oxide film disposed and annealed on the staircase pattern, wherein the doped silicon oxide film has a thickness of at least 5 μm,
wherein the doped silicon oxide film is deposited by a chemical vapor deposition (CVD) process using precursors for silicon oxide and a dopant selected from the group consisting of B, P, and Ge,
wherein each of the precursors for the dopant is selected from the group consisting of triethylborate (TEB), triethylphosphate (TEPO), and an organogermanium compound, and
wherein the doped silicon oxide film disposed and annealed on the staircase pattern exhibits substantially zero as-deposited stress, substantially zero stress shift post-anneal, and substantially zero shrinkage post-anneal.

13. The semiconductor device of claim 12 , wherein the doped silicon oxide film has a dopant concentration in the range of up to about 10 wt % of the film; or 0.5 to 10%; or 2-5%; or 2.5-3.5%.

14. The semiconductor device of claim 13 , wherein the doped silicon oxide film has a dopant concentration in the range of about 0 to 10 wt % of the film B, 0 to 10% P, 0 to 10% Ge.

15. The semiconductor device of claim 12 , wherein the doped silicon oxide film has a thickness of at least 10 μm.

16. An apparatus for processing substrates, the apparatus comprising:
a process chamber having a chuck;
a gas source connected with the process chambers and associated flow-control hardware;
substrate handling hardware; and
a controller having a processor and a memory, wherein:
the processor and the memory are communicatively connected with one another,
the processor is at least operatively connected with the flow-control and substrate handling hardware, and
the memory stores computer-executable instructions for controlling the processor to at least control the flow-control hardware and substrate handling hardware by:
providing a patterned semiconductor substrate;
depositing on a patterned semiconductor substrate disposed in the chamber a doped silicon oxide film having a thickness of at least 5 μm; and
annealing the doped silicon oxide film to a temperature above the film glass transition temperature,
wherein the doped silicon oxide film is deposited by a chemical vapor deposition (CVD) process using precursors for silicon oxide and a dopant selected from the group consisting of B, P, and Ge, and
wherein each of the precursors for the dopant is selected from the group consisting of triethylborate (TEB), triethylphosphate (TEPO), and an organogermanium compound.

17. The apparatus of claim 16 , wherein the annealing of the doped silicon oxide film causes reflow of the film to occur.

Assignees

• Lam Res Corp

Inventors

• Bayati Reza
• Van Schravendijk Bart J
• Church Jonathan
• Fox Keith

Classifications

• H10P14/6548

  by forming intermediate materials, e.g. capping layers or diffusion barriers · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H10P14/6923 Primary

  the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG · CPC title

• H10P14/6686

  the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane · CPC title

• H10P14/6922

  the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC · CPC title