Driving circuit, driving method, driving module and display device

Patent metadata

Field	Value
Publication number	US-12340753-B2
Application number	US-202318577408-A
Country	US
Kind code	B2
Filing date	Mar 29, 2023
Priority date	Mar 29, 2023
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A driving circuit, a driving method, a driving module and a display device are provided. The driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit, a voltage control circuit and a third control node control circuit. The third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.

First claim

What is claimed is:

1. A driving circuit, comprising a driving signal generation circuit, an output control circuit, a gating circuit, a voltage control circuit, an output circuit and a third control node control circuit; wherein
the driving signal generation circuit is electrically connected to a first control node, a second control node and an Nth stage of driving signal output terminal respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first control node and a potential of the second control node; N is a positive integer;
the output control circuit is electrically connected to a first node, the first control node and a second node respectively, and is configured to control to connect the first control node and the second node under the control of a potential of the first node;
the gating circuit is electrically connected to a gating control terminal, a gating input terminal and the first node respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first node under the control of a gating control signal provided by the gating control terminal;
the voltage control circuit is electrically connected to the first node and the second node respectively, and is configured to control a potential of the second node according to the potential of the first node;
the output circuit is electrically connected to the second node, a third control node, and an Nth stage of output driving terminal respectively, and is configured to generate and output an Nth stage of output driving signal through the Nth stage of output driving terminal under the control of the potential of the second node and a potential of the third control node;
the third control node control circuit is electrically connected to the first node and the third control node respectively, and is configured to control the potential of the third control node according to the potential of the first node.

2. The driving circuit according to claim 1 , further comprising a third node control circuit and a fourth node control circuit; wherein
the third node control circuit is configured to control a potential of a third node;
the fourth node control circuit is configured to control a potential of a fourth node;
the third control node control circuit is respectively connected to the third node, the first node,
the fourth node, a fifth node, a sixth node, the third control node, a first voltage terminal, a second voltage terminal and a first clock signal terminal, and is configured to control to connect the first node and the second voltage terminal under the control of the potential of the third node, and control to connect the fourth node and the fifth node under the control of the potential of the first node, and control the potential of the third control node according to a potential of the fifth node, control to connect the sixth node and the first voltage terminal under the control of the potential of the third node, control to connect the sixth node and the first clock signal terminal under the control of the potential of the fifth node, and control the potential of the fifth node according to a potential of the sixth node.

3. The driving circuit according to claim 2 , wherein the third control node control circuit includes a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, a fourth control sub-circuit and a fifth control sub-circuit;
the first control sub-circuit is electrically connected to the third node, the first node and the second voltage terminal respectively, and is configured to control to connect the first node and the second voltage terminal under the control of the potential of the third node;
the second control sub-circuit is electrically connected to the first node, the fourth node and the fifth node respectively, and is configured to control to connect the fourth node and the fifth node under the control of the potential of the first node;
the third control sub-circuit is electrically connected to the third node, the first voltage terminal, the sixth node and the first clock signal terminal respectively, and is configured to control to connect the sixth node and the first voltage terminal under the control of the potential of the third node, and control to connect the sixth node and the first clock signal terminal under the control of the potential of the fifth node, control the potential of the fifth node according to the potential of the sixth node;
the fourth control sub-circuit is electrically connected to the third control node and the fifth node respectively, and is configured to control the potential of the third control node according to the potential of the fifth node;
the fifth control sub-circuit is electrically connected to the first node, a twelfth node and the third control node respectively, and is configured to control to connect the twelfth node and the third control node under the control of the potential of the first node.

4. The driving circuit according to claim 3 , wherein the first control sub-circuit includes a first transistor and the second control sub-circuit includes a second transistor;
a gate electrode of the first transistor is electrically connected to the third node, a first electrode of the first transistor is electrically connected to the second voltage terminal, and a second electrode of the first transistor is electrically connected to the first node;
a gate electrode of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to the fourth node, and a second electrode of the second transistor is electrically connected to the fifth node.

5. The driving circuit according to claim 3 , wherein the third control sub-circuit includes a third transistor, a fourth transistor and a first capacitor;
a gate electrode of the third transistor is electrically connected to the third node, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the sixth node;
a gate electrode of the fourth transistor is electrically connected to the fifth node, a first electrode of the fourth transistor is electrically connected to the sixth node, and a second electrode of the fourth transistor is electrically connected to the first clock signal terminal;
a first end of the first capacitor is electrically connected to the sixth node, and a second end of the first capacitor is electrically connected to the fifth node.

6. The driving circuit according to claim 3 , wherein the fourth control sub-circuit includes a fifth transistor;
a gate electrode of the fifth transistor is electrically connected to the fifth node, a first electrode of the fifth transistor is electrically connected to the fifth node, and a second electrode of the fifth transistor is electrically connected to the third control node;
the fifth control sub-circuit includes a control transistor;
a gate electrode of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the twelfth node, and a second electrode of the control transistor is electrically connected to the third control node.

7. The driving circuit according to claim 2 , wherein the third node control circuit is respectively connected to the third node, a tenth node, an eighth node, the first voltage terminal and the first clock signal terminal, is configured control to connect the third node and the first voltage terminal under the control of a potential of the

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yu Ziyang
• Hu Ming
• Jiang Zhiliang
• Qiu Haijun
• Ma Long
• Cheng Tianyi
• Wu Jianpeng
• Chen Wenbo
• Yan Qingqing
• Pan Xiangnan
• He Qing
• Gu Quanyong
• Zhao Pan

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title