Driving circuit, display substrate and display device

Patent metadata

Field	Value
Publication number	US-12217650-B2
Application number	US-202117778376-A
Country	US
Kind code	B2
Filing date	Jun 2, 2021
Priority date	Jun 2, 2021
Publication date	Feb 4, 2025
Grant date	Feb 4, 2025

Abstract

A driving circuit includes an output circuit, a first node reset circuit and a second node control capacitor; the output circuit controls a driving signal terminal to output a driving signal under the control of a potential of a first node; the first node reset circuit controls to reset the first node under the control of a potential of a second node; the second node control capacitor is electrically connected to the second node; a width-to-length ratio of an output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; and/or a width-to-length ratio of a first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; and/or, a capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value.

First claim

What is claimed is:

1. A driving circuit, comprising an output circuit, a first node reset circuit and a second node control capacitor; wherein
the output circuit is configured to control a driving signal terminal to output a driving signal under the control of a potential of a first node;
the first node reset circuit is configured to control to reset the first node under the control of a potential of a second node;
the second node control capacitor is electrically connected to the second node;
a width-to-length ratio of an output transistor included in the output circuit is less than or equal to a first predetermined width-to-length ratio; and/or a width-to-length ratio of a first node reset transistor included in the first node reset circuit is greater than or equal to a second predetermined width-to-length ratio; and/or, a capacitance value of the second node control capacitor is greater than or equal to a predetermined capacitance value;
a range of the first predetermined width-to-length ratio is greater than or equal to 150/3.8 and less than or equal to 230/3.8, and a range of the second predetermined width-to-length ratio is greater than or equal to 4/4.9 and less than or equal to 6/4.9; a range of the predetermined capacitance value is greater than or equal to 143fF and less than or equal to 243fF;
wherein the driving circuit further comprises a third node control circuit, a fourth node control circuit, a fifth node control circuit, a second node control circuit, a first node control circuit, and an output reset circuit;
the third node control circuit is respectively electrically connected to a second clock signal line, a first voltage line and a third node, and is configured to write a first voltage signal provided by the first voltage line into the third node under the control of a second clock signal provided by the second clock signal line;
the fourth node control circuit is respectively electrically connected to a sixth node, a third clock signal line and a fourth node, and is configured to control the third clock signal line to write a third clock signal into the fourth node under the control of a potential of the sixth node, and control a potential of the fourth node according to the potential of the sixth node;
the fifth node control circuit is electrically connected to the second clock signal line, a first clock signal line, an input terminal and a fifth node respectively, and is configured to control the input terminal to provide an input signal to the fifth node under the control of the second clock signal provided by the second clock signal line and a first clock signal provided by the first clock signal line;
the second node control circuit is respectively electrically connected to a third node, a seventh node, a second voltage line, a second node and a third clock signal line, and is configured to control to connect the seventh node and the second voltage line under the control of a potential of the third node, and control to connect the seventh node and the third clock signal line under the control of the potential of the second node;
a first electrode plate of the second node control capacitor is electrically connected to the seventh node, and a second electrode plate of the second node control capacitor is electrically connected to the second node;
the first node control circuit is respectively electrically connected to the fourth node, the third clock signal line and the first node, and is configured to control to connect the fourth node and the first node under the control of the third clock signal provided by the third clock signal line;
the output reset circuit is respectively electrically connected to the second node, the driving signal terminal and the first voltage line, and is configured to control to connect the driving signal terminal and the first voltage line under the control of the potential of the second node.

2. The driving circuit according to claim 1 , wherein the first predetermined width-to-length ratio is 210/3.8, the second predetermined width-to-length ratio is 5/4.9, and the predetermined capacitance value is 243fF.

3. The driving circuit according to claim 2 , wherein a control electrode of the output transistor is electrically connected to the first node, a first electrode of the output transistor is electrically connected to a first clock signal line, and a second electrode of the output transistor is electrically connected to the driving signal terminal;
a control electrode of the first node reset transistor is electrically connected to the second node, a first electrode of the first node reset transistor is electrically connected to the first node, and a second electrode of the first node reset transistor is electrically connected to the first clock signal line.

4. The driving circuit according to claim 1 , wherein a control electrode of the output transistor is electrically connected to the first node, a first electrode of the output transistor is electrically connected to a first clock signal line, and a second electrode of the output transistor is electrically connected to the driving signal terminal;
a control electrode of the first node reset transistor is electrically connected to the second node, a first electrode of the first node reset transistor is electrically connected to the first node, and a second electrode of the first node reset transistor is electrically connected to the first clock signal line.

5. The driving circuit according to claim 1 , wherein the third node and the sixth node are a same node; or,
the driving circuit further includes a first conduction control circuit; the first conduction control circuit is configured to control to connect the third node and the sixth node under the control of the first voltage signal provided by the first voltage line.

6. The driving circuit according to claim 1 , wherein the fifth node and the second node are a same node; or,
the driving circuit further includes a second conduction control circuit; the second conduction control circuit is configured to control to connect the fifth node and the second node under the control of the first voltage signal provided by the first voltage line.

7. The driving circuit according to claim 1 , wherein the third node control circuit includes a first transistor and a second transistor;
a control electrode of the first transistor is electrically connected to the second clock signal line, a first electrode of the first transistor is electrically connected to the first voltage line, and a second electrode of the first transistor is electrically connected to the third node;
a control electrode of the second transistor is electrically connected to the fifth node, a first electrode of the second transistor is electrically connected to the second clock signal line, and a second electrode of the second transistor is electrically connected to the third node;
the fourth node control circuit includes a third transistor and a first capacitor;
a control electrode of the third transistor is electrically connected to the sixth node, a first electrode of the third transistor is electrically connected to the third clock signal line, and a second electrode of the third transistor is electrically connected to the fourth node;
a first electrode plate of the first capacitor is electrically connected to the sixth node, and a second electrode plate of the first capacitor is electrically connected to the fourth node;
the fifth node control circuit includes a fourth transistor and a fifth transistor;
a control electrode of the fourth transistor is electrically connected to the first clock signal line, and a first electrode of the fourth transistor is electrically connected to an input end;
a control electrode of the fifth transistor is

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Li Meng
• Cheng Tianyi
• Huang Yao

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title