Storage controller, computational storage device, and operational method of computational storage device

Patent metadata

Field	Value
Publication number	US-12340120-B2
Application number	US-202318126595-A
Country	US
Kind code	B2
Filing date	Mar 27, 2023
Priority date	Jun 17, 2021
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A computational storage device includes a non-volatile memory (NVM) device; and a storage controller configured to control the NVM device. The storage controller includes: a computation processor configured to execute an internal application to generate an internal command; a host interface circuit configured to receive a host command from an external host device, to receive the internal command from the computation processor, and to individually process the received host command and the received internal command; a flash translation layer (FTL) configured to perform an address mapping operation based on a result of the processing of the host interface circuit; and a memory interface circuit configured to control the NVM device based on the address mapping operation of the FTL.

First claim

What is claimed is:

1. A computational storage device comprising:
a non-volatile memory (NVM) device;
a computational processor configured to generate an internal command by executing an internal application; and
a storage controller configured to receive the internal command from the computational processor, to access the NVM device in response the received internal command, to receive a host command from an external host device, and to access the NVM device in response to the received host command,
wherein the storage controller includes:
a host interface circuit configured to receive both the internal command and the host command; and
a flash translation layer (FTL) circuit configured to perform a first address mapping based on the internal command received from the host interface circuit and perform a second address mapping based on the host command received from the host interface circuit, and

wherein the FTL circuit comprises:
a first hardware circuit that translates a logical address into a physical address for each of the first address mapping and the second address mapping;
a read buffer circuit configured to automate a read path associated with a read operation on the NVM device;
a write buffer circuit configured to automate a write path associated with a write operation on the NVM device; and
a second hardware circuit that processes errors occurring during the translation from the logical address to the physical address.

2. The computational storage device of claim 1 , further comprising:
a first memory configured to be accessed by the computational processor; and
a second memory configured to be accessed by the storage controller.

3. The computational storage device of claim 1 , further comprising:
a shared memory configured to be accessed by both the computational processor and the storage controller.

4. The computational storage device of claim 1 , further comprising:
a first memory configured to be accessed by the storage controller,
wherein the computational processor is further configured to access the first memory through the storage controller.

5. The computational storage device of claim 1 , wherein the host command is provided to the storage controller through the computational processor.

6. The computational storage device of claim 1 , wherein the computational processor is further configured to communicate with the external host device through a first interface, and
wherein the storage controller is further configured to communicate with the external host device through a second interface different from the first interface.

7. The computational storage device of claim 1 , further comprising:
a peripheral component interconnect express (PCIe) switch,
wherein the computational processor and the storage controller are further configured to communicate with the external host device through the PCIe switch.

8. The computational storage device of claim 1 , wherein the storage controller further comprises:
a non-volatile memory interface circuit configured to access the NVM device based on the first address mapping and the second address mapping.

9. A computational storage device comprising:
a non-volatile memory (NVM) device;
a computational processor configured to generate an internal command by executing an internal application;
a host interface circuit configured to receive a host command from an external host device, receive the internal command from the computational processor, process the received host command, and process the received the internal command;
a flash translation layer (FTL) circuit configured to perform a first address mapping for the processed host command, and perform a second address mapping for the processed internal command; and
a memory interface circuit configured to access the NVM device based on the first address mapping and access the NVM device based on the second address mapping,
wherein the FTL circuit comprises:
a first hardware circuit that translates a logical address into a physical address for each of the first address mapping and the second address mapping;
a read buffer circuit configured to automate a read path associated with a read operation on the NVM device;
a write buffer circuit configured to automate a write path associated with a write operation on the NVM device; and
a second hardware circuit that processes errors occurring during the translation from the logical address to the physical address.

10. The computational storage device of claim 9 , wherein the host interface circuit comprises:
a physical port configured to receive the host command from the external host device; and
a non-volatile memory express (NVMe) processor configured to process the received host command and the received the internal command.

11. The computational storage device of claim 10 , wherein the physical port is further configured to receive the internal command from the computational processor, and
the NVMe processor is further configured to receive the internal command through the physical port.

12. The computational storage device of claim 10 , wherein the NVMe processor is further configured to receive the internal command through a system bus.

13. The computational storage device of claim 10 , wherein the physical port is further configured to receive an execution command from the external host device, and transfer the execution command to the computational processor, and
the computational processor executes the internal application in response to receiving the transferred execution command and executes the internal command based on the execution of the internal application.

14. The computational storage device of claim 10 , wherein the physical port is further configured to receive an execution command from the external host device,
the NVMe processor is further configured to receive the execution command from the physical port and transfer the execution command to the computational processor, and
the computational processor executes the internal application in response to receiving the transferred execution command and executes the internal command based on the execution of the internal application.

15. The computational storage device of claim 9 , further comprises:
a controller memory configured to store the internal application.

16. A computational storage device comprising:
a non-volatile memory device; and
a storage controller configured to receive a host command from an external host device and process the host command through a first I/O path on the storage controller,
wherein the storage controller includes a computational processor configured to execute an internal application to generate an internal command,
wherein the storage controller is further configured to process the internal command through a second I/O path on the storage controller,
wherein both the first I/O path and the second I/O path include a host interface circuit, a flash translation layer (FTL) circuit, and a non-volatile memory interface circuit,
wherein the storage controller comprises a flash translation layer (FTL) circuit configured to perform a first address mapping based on the processed internal command and perform a second address mapping based on the processed host command, and
wherein the FTL circuit comprises:
a first hardware circuit that translates a logical address into a physical address for each of the first address mapping and the second address mapping;
a read buffer circuit configured to automate a read path associated with a read operation on the NVM device;
a write buffer

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Hwang
• Heo Wan

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title