Semiconductor device

Patent metadata

Field	Value
Publication number	US-12336267-B2
Application number	US-202117472465-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 17, 2020
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A semiconductor device includes first and second semiconductor layers of a first conductivity type, a third semiconductor layer of a second conductivity type, a plurality of electrodes, and a first insulating film. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer with a first surface at a side opposite to the first semiconductor layer. The electrodes extend from the first surface into the second semiconductor layer. A first insulating film provided between the second and third semiconductor layers and each of electrodes. The electrodes include first and second electrode groups. The first electrode group is arranged in one column in the first direction and apart from each other by a first distance. The first and second electrode groups are apart from each other by a second distance in the second direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, the second semiconductor layer including a first-conductivity-type impurity with a lower concentration than a concentration of a first-conductivity-type impurity in the first semiconductor layer;
a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, the third semiconductor layer including a first surface at a side opposite to the second semiconductor layer, the first surface extending in a first direction and a second direction crossing the first direction;
a plurality of electrodes provided on the second semiconductor layer, the plurality of electrodes respectively extending inside trenches, the trenches each having depths enough to extend from the first surface into the second semiconductor layer; and
a first insulating film provided between the third semiconductor layer and one of the plurality of electrodes and between the second semiconductor layer and the one of the plurality of electrodes,
the plurality of electrodes including a first electrode group and a second electrode group,
the first electrode group being arranged in one column in the first direction and apart from each other by a first distance,
the second electrode group being arranged in another column in the first direction and apart from each other by the first distance,
the first electrode group and the second electrode group being apart from each other by a second distance in the second direction, the first distance being greater than the second distance,
each of the trenches having a first length in the first direction, and a second length in the second direction,
the second length being less than the first length, and
the first distance being less than the first length in the first and second electrode groups.

2. The device according to claim 1 , wherein
the first distance is provided such that a portion of the second semiconductor layer between two adjacent electrodes of the plurality of electrodes is depleted when a prescribed voltage is applied between the first semiconductor layer and the third semiconductor layer.

3. The device according to claim 1 , wherein
a current path of the second semiconductor layer positioned between the plurality of electrodes is pinched off when a prescribed voltage is applied between the first semiconductor layer and the third semiconductor layer and between the first semiconductor layer and the plurality of electrodes.

4. The device according to claim 1 , wherein
the first distance is not more than 2 micrometers.

5. The device according to claim 1 , wherein
a surface area of the third semiconductor layer at the first surface is greater than a sum of a surface area of the plurality of first insulating films and a surface area of the plurality of electrodes at a level same as a level of the first surface.

6. The device according to claim 1 , wherein
the trench has a first length in the first direction, and a second length in the second direction, and
the second length is less than the first length.

7. The device according to claim 1 , wherein
the first electrode group and the second electrode group are adjacent in the second direction, and
each electrode of the second electrode group and a space between adjacent electrodes of the first electrode group are arranged in the second direction.

8. The device according to claim 7 , wherein
the trench has a polygonal shape in a cross-section parallel to the first surface.

9. The device according to claim 1 , wherein
no semiconductor layer of the first conductivity type is provided on the third semiconductor layer.

10. The device according to claim 1 , wherein
the semiconductor device is a diode.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Itokazu Hiroko
• Matsudai Tomoko
• Iwakaji Yoko
• Motai Takako
• Kawamura Keiko
• Fuse Kaori

Classifications

• H10D84/617

  Combinations of vertical BJTs and only diodes · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D12/481

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D64/112

  comprising multiple field plate segments · CPC title

• H10D8/422 Primary

  PN diodes having the PN junctions in mesas · CPC title