Semiconductor device

Patent metadata

Field	Value
Publication number	US-2019081163-A1
Application number	US-201816188533-A
Country	US
Kind code	A1
Filing date	Nov 13, 2018
Priority date	May 17, 2016
Publication date	Mar 14, 2019
Grant date	—

Abstract

A semiconductor device includes a single semiconductor substrate on which an IGBT region including an IGBT element and an FWD region including a FWD element are formed. In the semiconductor device, a cathode layer is formed with a carrier injection layer, which is electrically connected to a second electrode and has a PN junction with a field stop layer. When a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current is flowing through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer.

First claim

1 . A semiconductor device provided with an IGBT region having an IGBT element and an FWD region having an FWD element, the semiconductor device comprising:
a semiconductor substrate having the IGBT region and the FWD region, wherein the semiconductor substrate includes:
a drift layer having a first-type conductivity;
a base layer having a second-type conductivity and formed on the drift layer;
an emitter region having the first-type conductivity configured to be a surface layer portion of the base layer, and configured to be isolated from the drift layer to interpose the base layer between the drift layer and the emitter region, the emitter region having a higher impurity concentration as compared with the drift layer;
a gate insulation film arranged on a surface of the base layer, which is between the emitter region and the drift layer;
a gate electrode arranged on the gate insulation film;
a field stop layer having the first-type conductivity facing the base layer to interpose the drift layer between the field stop layer and the base layer, the field stop layer having a higher impurity concentration as compared with the drift layer;
a collector layer having the second-type conductivity facing the drift layer to interpose the field stop layer between the collector layer and the drift layer;
a cathode layer having the first-type conductivity facing the drift layer to interpose the field stop layer between the cathode layer and the drift layer, the cathode layer being adjacent to the collector layer;
a first electrode electrically connected to the base layer and the emitter region; and
a second electrode electrically connected to the collector layer and the cathode layer,
wherein the cathode layer is formed with a single carrier injection layer having the second-type conductivity at a position isolated from the collector layer, wherein the single carrier injection layer has a PN junction with the field stop layer and is electrically connected to the second electrode, and wherein, when a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current flows through the FWD element, a second carrier is injected from the second electrode into the drift layer through the carrier injection layer.

2 . The semiconductor device according to claim 1 ,
wherein the carrier injection layer is formed to include the center of the cathode layer.

3 . A semiconductor device provided with an IGBT region having an IGBT element and an FWD region having an FWD element, the semiconductor device comprising:
a semiconductor substrate having the IGBT region and the FWD region, wherein the semiconductor substrate includes:
a drift layer having a first-type conductivity;
a base layer having a second-type conductivity and formed on the drift layer;
an emitter region having the first-type conductivity configured to be a surface layer portion of the base layer, and configured to be isolated from the drift layer to interpose the base layer between the drift layer and the emitter region, the emitter region having a higher impurity concentration as compared with the drift layer;
a gate insulation film arranged on a surface of the base layer, which is between the emitter region and the drift layer;
a gate electrode arranged on the gate insulation film;
a field stop layer having the first-type conductivity facing the base layer to interpose the drift layer between the field stop layer and the base layer, the field stop layer having a higher impurity concentration as compared with the drift layer;
a collector layer having the second-type conductivity facing the drift layer to interpose the field stop layer between the collector layer and the drift layer;
a cathode layer having the first-type conductivity facing the drift layer to interpose the field stop layer between the cathode layer and the drift layer, the cathode layer being adjacent to the collector layer;
a first electrode electrically connected to the base layer and the emitter region; and
a second electrode electrically connected to the collector layer and the cathode layer,
wherein the cathode layer is formed with a single carrier injection layer having the second-type conductivity at a position isolated from the collector layer, wherein the carrier injection layer has a PN junction with the field stop layer and is electrically connected to the second electrode, wherein, when a first carrier in the FWD element passes through the field stop layer on the carrier injection layer and flows into the cathode layer in a situation where a forward-biased current is cut off from a state in which the forward-biased current flows through the FWD element, a second carrier is injected from the second electrode into a drift layer through the carrier injection layer, and wherein the carrier injection layer is formed to include the center of the cathode layer.

4 . The semiconductor device according to claim 1 ,
wherein the carrier injection layer is in an extension direction parallel to one of planar directions of the semiconductor substrate, wherein the impurity concentration of the field stop layer refers to Nfs in a unit of cm −3 , wherein the carrier injection layer has a length in a direction perpendicular to the extension direction of the carrier injection layer and in a direction parallel to the one of planar directions of the semiconductor substrate, wherein the length of the carrier injection layer refers to W in a unit of μm, and wherein the carrier injection layer is configured to satisfy W>6.8×10 −16 ×Nfs+20.

Assignees

• Denso Corp

Inventors

• MIZUKAMI Taku

Classifications

• H01L29/8611

  Electricity · mapped topic

• H01L29/7394

  Electricity · mapped topic

• H01L29/083

  Electricity · mapped topic

• H01L29/7397 Primary

  Electricity · mapped topic

• H10D84/811 Primary

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title