Stable scalable digital frequency reference

Patent metadata

Field	Value
Publication number	US-12334940-B2
Application number	US-202017776322-A
Country	US
Kind code	B2
Filing date	Nov 13, 2020
Priority date	Nov 13, 2019
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A method for timing aperture synthesis arrays comprising the steps of: (a) coupling a plurality of independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency; (b) digitally synchronizing the plurality of independent crystal oscillators in phase; (c) combining the unique output frequencies; and (d) obtaining a stable digital reference signal for timing at least one remote radio device of the aperture synthesis array.

First claim

The invention claimed is:

1. A method for timing aperture synthesis arrays comprising
(a) coupling a plurality of three or more independent crystal oscillators, each of the plurality of independent crystal oscillators having a unique output frequency;
(b) digitally synchronizing the plurality of three or more independent crystal oscillators in phase;
(c) combining the unique output frequencies; and
(d) obtaining a stable digital reference signal for timing at least one remote radio device.

2. The method of claim 1 , wherein the stable digital reference signal is at least one of scalable and stable relative to a common and unstable frequency reference signal.

3. The method of claim 2 , wherein the stable digital reference signal is employed in timing at least one remote device.

4. The method of claim 3 , wherein the at least one remote device is a radio telescope.

5. The method of claim 2 , wherein the scalable stable digital frequency reference is used in conjunction with a packet-switched network communication link.

6. The method of claim 2 , wherein the scalable stable digital frequency reference is used in conjunction with a non-real-time communication link.

Assignees

• Nat Res Council Canada

Inventors

• Carlson Brent

Classifications

• H03L7/24

  using a reference signal directly applied to the generator · CPC title

• H03L7/141

  the phase-locked loop controlling several oscillators in turn · CPC title

• H03B21/04

  using several similar stages · CPC title

• H03B21/02

  by plural beating, i.e. for frequency synthesis {; Beating in combination with multiplication or division of frequency (digital frequency synthesis using a ROM G06F1/02; digital frequency synthesis in general H03K; indirect frequency synthesis using a PLL H03L7/16)} · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title