Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI)

Patent metadata

Field	Value
Publication number	US-12334447-B2
Application number	US-201916455688-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Jun 27, 2019
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Embodiments described herein relate to lithographically defined vertical interconnect accesses (litho-vias) for a bridge die first level interconnect (FLI) and techniques of fabricating such litho-vias. In one example, a package substrate comprises a bridge die embedded in the package substrate; a first contact pad outside a perimeter of the bridge die; a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via; a third pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via. The first contact pad has a surface finish disposed thereon. A first protruded interconnect structure is positioned on the first via and a second protruded interconnect structure is positioned on the second via. Each of the first and second vias have sidewalls that are substantially vertical.

First claim

The invention claimed is:

1. A package substrate, comprising:
a bridge die embedded in the package substrate;
a first contact pad outside a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the first via having substantially vertical sidewalls, and the second contact pad having a protruded interconnect structure positioned thereon, wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer; and
a third contact pad outside the perimeter of the bridge die, the third contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the third contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the first via having substantially vertical sidewalls, and the third contact pad having a protruded interconnect structure positioned thereon, wherein the third contact pad has an uppermost surface at the same level as the uppermost surface of the second contact pad, and wherein the first via and the lower contact pad coupled to the third contact pad are in the dielectric layer, and the third contact pad is above the dielectric layer.

2. The package substrate of claim 1 , further comprising:
a fourth contact pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a via having substantially vertical sidewalls, the fourth contact pad having a protruded interconnect structure positioned thereon.

3. The package substrate of claim 2 , wherein a pitch between the first and second vias is less than or equal to 50 microns (μm).

4. The package substrate of claim 2 , further comprising:
a solder resist layer surrounding the first and second vias.

5. The package substrate of claim 1 , wherein the surface finish comprises electroless nickel electroless palladium immersion gold (ENEPIG).

6. The package substrate of claim 1 , wherein the protruded interconnect structure comprises one or more of nickel, tin, and copper.

7. The package substrate of claim 1 , wherein the first contact pad is a die side capacitor pad.

8. A semiconductor package, comprising:
a package substrate;
a bridge die embedded in the package substrate;
a first contact pad outside of a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, wherein a first protruded interconnect structure is positioned on the first via, and wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer;
a third contact pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via, wherein a second protruded interconnect structure is positioned on the second via;
a fourth contact pad outside the perimeter of the bridge die, the fourth contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the fourth contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the fourth contact pad having a protruded interconnect structure positioned thereon, wherein the fourth contact pad has an uppermost surface at the same level as the uppermost surface of the second contact pad, and wherein the first via and the lower contact pad coupled to the fourth contact pad are in the dielectric layer, and the fourth contact pad is above the dielectric layer;
a first semiconductor die coupled to the package substrate by the first protruded interconnect structure; and
a second semiconductor die coupled to the package substrate by the second protruded interconnect structure.

9. The semiconductor package of claim 8 , wherein a pitch between the first and second vias is less than or equal to 50 microns (μm).

10. The semiconductor package of claim 8 , wherein the first and second protruded interconnect structures directly contact the second and third contact pads, respectively.

11. The semiconductor package of claim 8 , further comprising:
a solder resist layer surrounding the first and second vias.

12. The semiconductor package of claim 8 , wherein the surface finish comprises electroless nickel electroless palladium immersion gold (ENEPIG).

13. The semiconductor package of claim 8 , wherein each of the first and second protruded interconnect structures comprises one or more of nickel, copper, and tin.

14. A packaged system, comprising:
a printed circuit board (PCB); and
a semiconductor package coupled to the PCB, the semiconductor package comprising:
a package substrate;
a bridge die embedded in the package substrate;
a first contact pad outside a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, wherein a first protruded interconnect structure is positioned on the first via, and wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer;
a third contact pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via, wherein a second protruded interconnect structure is positioned on the second via;
a fourth contact pad outside the perimeter of the bridge die, the fourth contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the fourth contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the fourth contact pad having a protruded interconnect structure positioned thereon, wherein the fourth contact pad has an uppermost surface at the same level as the uppermost surface of the second co

Assignees

• Intel Corp

Inventors

• Darmawikarta Kristof
• Ibrahim Tarek
• Alur Siddharth
• Jain Rahul
• Chen Haobo

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/687

  characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage · CPC title