Semiconductor device

Patent metadata

Field	Value
Publication number	US-12334438-B2
Application number	US-202217742619-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	Jul 19, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate including a first region and a second region;
first metal lines spaced apart from each other at a first interval on the first region;
second metal lines spaced apart from each other at a second interval on the second region, the second interval being smaller than the first interval; and
a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including:
sidewall parts that cover sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric material,
upper parts that cover top surfaces of the first metal lines and the second metal lines, and
an air gap defined by the sidewall parts between the second metal lines,

wherein a density of pores in the sidewall parts is greater than a density of pores in the upper parts.

2. The semiconductor device as claimed in claim 1 , wherein the upper parts include a non-porous dielectric material.

3. The semiconductor device as claimed in claim 1 , wherein the sidewall parts of the passivation layer include pores that have directionality in a certain direction.

4. The semiconductor device as claimed in claim 1 , further comprising a lower layer between the semiconductor substrate and the first and second metal lines,
wherein the passivation layer further includes a lower part between adjacent ones of the first metal lines and between adjacent ones of the second metal lines, the lower part covering a top surface of the lower layer, and
wherein a density of pores in the lower part of the passivation layer is less than a density of pores in the sidewall parts of the passivation layer.

5. The semiconductor device as claimed in claim 1 , wherein a vertex of the air gap is at a level higher than levels of the top surfaces of the first metal lines and the second metal lines.

6. The semiconductor device as claimed in claim 1 , further comprising a lower layer between the semiconductor substrate and the first and second metal lines,
wherein the air gap has lateral surfaces adjacent to the sidewalls of the second metal lines and a bottom surface adjacent to a top surface of the lower layer, and
wherein a surface roughness on the lateral surfaces is greater than a surface roughness on the bottom surface.

7. The semiconductor device as claimed in claim 1 , wherein the passivation layer has a first thickness between the first metal lines and a second thickness on the first metal lines, the second thickness being less than the first thickness.

8. The semiconductor device as claimed in claim 1 , further comprising a metal capping pattern between the passivation layer and the top surface of each of the first metal lines and the second metal lines, the upper parts of the passivation layer being in contact with the metal capping pattern.

9. The semiconductor device as claimed in claim 1 , wherein the passivation layer includes an oxide layer containing hydrogen.

10. The semiconductor device as claimed in claim 1 , wherein a thickness of the passivation layer between the first metal lines is greater than a thickness of the passivation layer between the second metal lines.

11. A semiconductor device, comprising:
metal lines on a semiconductor substrate; and
a passivation layer that covers the metal lines, the passivation layer including:
sidewall parts that cover sidewalls of the metal lines, and

upper parts that cover top surfaces of the metal lines, wherein a density of pores in the sidewall parts is greater than a density of pores in the upper parts.

12. The semiconductor device as claimed in claim 11 , wherein the passivation layer has an air gap between the metal lines, the air gap being defined by the sidewall parts.

13. The semiconductor device as claimed in claim 11 , wherein the sidewall parts have a thickness of about 50 Å to about 2,000 Å on the sidewalls of the metal lines.

14. The semiconductor device as claimed in claim 11 , wherein the passivation layer includes an oxide layer containing hydrogen.

15. The semiconductor device as claimed in claim 11 , wherein the passivation layer further includes a gap-fill part that fills a space between the metal lines, a density of pores in the gap-fill part is less than the density of pores in the sidewall parts.

16. A semiconductor device, comprising:
a first metal line that has a first width on a lower layer;
a second metal line that has a second width less than the first width on the lower layer;
a third metal line that has the second width on the lower layer, the third metal line being between the first metal line and the second metal line; and
a passivation layer that covers the first metal line, the second metal line, and the third metal line, the passivation layer including:
a porous region adjacent to sidewalls of each of the first metal line, the second metal line, and the third metal line, and
a non-porous region adjacent to a top surface of each of the first metal line, the second metal line, and the third metal line.

17. The semiconductor device as claimed in claim 16 , wherein the passivation layer has an air gap between the second and third metal lines.

18. The semiconductor device as claimed in claim 17 , wherein the air gap has lateral surfaces adjacent to the sidewalls of the second metal line and the third metal line, and a bottom surface adjacent to a top surface of the lower layer, a surface roughness on the lateral surfaces is greater than a surface roughness on the bottom surface.

19. The semiconductor device as claimed in claim 17 , wherein a vertex of the air gap is at a level higher than levels of the top surfaces of the first metal line, the second metal line, and the third metal line.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Minsung
• Mun Hyoungyol
• Cho Sungdong
• Cho Wonhee

Classifications

• H10W20/072 Primary

  of dielectric parts comprising air gaps · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title