Patterning method for low-k inter-metal dielectrics and associated semiconductor device

Patent metadata

Field	Value
Publication number	US-9401304-B2
Application number	US-201414260867-A
Country	US
Kind code	B2
Filing date	Apr 24, 2014
Priority date	Apr 24, 2014
Publication date	Jul 26, 2016
Grant date	Jul 26, 2016

Abstract

Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure, comprising:
patterning an insulation layer carried on a substrate, the patterning forms at least first and second ridges in the insulation layer which are spaced-apart from one another;
slimming the first and second ridges to form first and second slimmed ridges, respectively;
depositing an inter-metal material, the inter-metal material conforming to a shape of the first and second slimmed ridges;
performing an etching operation, the etching operation etches through portions of the inter-metal material, resulting in a first raised structure comprising portions of the inter-metal material on opposing sides of the first slimmed ridge and a second raised structure comprising portions of the inter-metal material on opposing sides of the second slimmed ridge;
providing a barrier metal layer, the barrier metal layer conforming to a shape of the first and second raised structures;
providing a metal filler over the barrier metal layer, the metal filler extending above and between the first and second raised structures; and
performing a planarizing operation, the planarizing operation results in:
planarizing of the first and second raised structures, respectively,
planarizing of the metal filler to form a remaining portion of the metal filler as an elongated conductive line which extends between, but not above, the first and second raised structures,
removal of portions of the inter-metal material and the barrier metal layer above the first and second slimmed ridges, and
removal of top portions of the slimmed ridges, wherein the planarizing operation stops at a selected elevation at which top surfaces of the first and second slimmed ridges, top surfaces of the inter-metal material, and top surfaces of the barrier metal layer are exposed.

2. The method of claim 1 , wherein:
the inter-metal material comprises a film having a dielectric constant of less than 3.9.

3. The method of claim 1 , wherein the planarizing operation stops at a selected elevation at which top surfaces of the first and second slimmed ridges, top surfaces of the inter-metal material, and top surfaces of the barrier metal layer are exposed, the method further comprising:
depositing a porous layer above the top surfaces of the first and second slimmed ridges, the top surfaces of the inter-metal material, and the top surfaces of the barrier metal layer; and
applying heat to cause diffusion of the portions of the inter-metal material on the opposing sides of the first slimmed ridge through the porous layer, resulting in air gaps on the opposing sides of the first slimmed ridge.

4. The method of claim 3 , wherein:
the inter-metal material is a sacrificial material, and the sacrificial material comprises a thermally-degradable polymer.

5. The method of claim 1 , wherein:
the first slimmed ridge comprises a peak and opposing concave sidewalls extending down from the peak of the first slimmed ridge to a base of the first slimmed ridge; and
the second slimmed ridge comprises a peak and opposing concave sidewalls extending down from the peak of the second slimmed ridge to a base of the second slimmed ridge.

6. The method of claim 5 , wherein:
the portions of the inter-metal material on the opposing sides of the first slimmed ridge comprise convex sidewalls which correspond to the concave sidewalls of the first slimmed ridge; and
the portions of the inter-metal material on the opposing sides of the second slimmed ridge comprise convex sidewalls which correspond to the concave sidewalls of the second slimmed ridge.

7. The method of claim 1 , further comprising:
providing a metal seed layer over the barrier metal layer, the metal filler is provided over the metal seed layer, and the planarizing operation removes portions of the metal seed layer above the first and second slimmed ridges.

8. The method of claim 1 , wherein:
the providing the metal filler comprises depositing the metal filler using physical vapor deposition (PVD) and reflowing the metal filler.

9. The method of claim 1 , wherein:
the metal filler comprises copper and the insulation layer comprises SiO2.

10. The method of claim 1 , wherein:
the elongated conductive line comprises a bit line in a memory device.

11. The method of claim 1 , wherein:
the inter-metal material comprises an aerogel.

12. A method for fabricating a semiconductor structure, comprising:
patterning an insulation layer carried on a substrate, the patterning forms a first ridge in the insulation layer;
slimming the first ridge to form a first slimmed ridge;
depositing an inter-metal material, the inter-metal material conforming to a shape of the first slimmed ridge;
performing an etching operation, the etching operation etches through portions of the inter-metal material, resulting in a first raised structure comprising portions of the inter-metal material on opposing sides of the first slimmed ridge;
providing a barrier metal layer, the barrier metal layer conforming to a shape of the first raised structure;
providing a metal filler over the barrier metal layer, the metal filler extending over the first raised structure, on one side of the first raised structure and on another side of the first raised structure; and
performing a planarizing operation, the planarizing operation results in planarizing of the metal filler to form one remaining portion of the metal filler as a first elongated conductive line on the one side of the first raised structure and another remaining portion of the metal filler as a second elongated conductive line on the another side of the first raised structure, the planarizing operation stops at a selected elevation at which a top portion of the first slimmed ridge is exposed, and top surfaces of the first and second elongated conductive line are at the selected elevation.

13. The method of claim 12 , wherein:
the inter-metal material comprises a film having a dielectric constant of less than 3.9.

14. The method of claim 12 , wherein the inter-metal material is a sacrificial material, the method further comprising:
depositing a porous layer; and
applying heat to cause diffusion of the portions of the inter-metal material on the opposing sides of the first slimmed ridge through the porous layer, resulting in air gaps on the opposing sides of the first slimmed ridge.

15. The method of claim 1 , wherein:
the metal filler is provided over portions of the inter-metal material and the barrier metal layer which are between the first and second slimmed ridges.

16. The method of claim 1 , wherein:
a top of the conductive line is at the selected elevation; and
a bottom of the conductive line is above the portions of the inter-metal material and the barrier metal layer which are between the first and second slimmed ridges.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Fukuo Noritaka

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title