Interconnect structure including graphite and method forming same

Patent metadata

Field	Value
Publication number	US-12334397-B2
Application number	US-202117382001-A
Country	US
Kind code	B2
Filing date	Jul 21, 2021
Priority date	May 13, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

First claim

What is claimed is:

1. A method comprising:
forming a first conductive feature;
depositing a graphite layer over the first conductive feature;
patterning the graphite layer to form a graphite conductive feature;
depositing a dielectric spacer layer on the graphite layer;
depositing a first dielectric layer over the dielectric spacer layer;
planarizing the first dielectric layer, wherein the planarizing the first dielectric layer stops on a top surface of a horizontal portion of the dielectric spacer layer, with the horizontal portion being overlapping the graphite conductive feature;
forming a second dielectric layer over the first dielectric layer; and
forming a second conductive feature in the second dielectric layer, wherein the second conductive feature is over the graphite conductive feature and penetrates through the horizontal portion of the dielectric spacer layer to be electrically connected to the graphite conductive feature.

2. The method of claim 1 , wherein after the dielectric spacer layer is formed, a surface portion of the graphite conductive feature has been converted into an amorphous layer, and the dielectric spacer layer is deposited on the amorphous layer.

3. The method of claim 2 , wherein in the planarizing, a horizontal portion of the amorphous layer is removed, with the horizontal portion being overlapping the graphite conductive feature.

4. The method of claim 1 , wherein the patterning the graphite layer further forms a graphite seal ring.

5. The method of claim 4 further comprising forming a conductive ring in the second dielectric layer, wherein the conductive ring is over and electrically connected to the graphite seal ring.

6. The method of claim 1 , wherein the depositing the graphite layer is performed using plasma enhanced chemical vapor deposition.

7. The method of claim 1 , wherein the second conductive feature is formed using a damascene process, and the second conductive feature comprises copper.

8. The method of claim 1 further comprising depositing an etch stop layer over the first dielectric layer and the graphite conductive feature, wherein the second dielectric layer is deposited over the etch stop layer.

9. A method comprising:
forming a graphite conductive feature over and electrically coupling to a first conductive feature;
forming a dielectric spacer layer, wherein the dielectric spacer layer comprises sidewall portions on sidewalls of the graphite conductive feature;
forming a first dielectric layer, wherein the sidewall portions of the dielectric spacer layer are in the first dielectric layer;
planarizing the first dielectric layer and the dielectric spacer layer to remove a horizontal portion of the dielectric spacer layer that overlaps the graphite conductive feature;
depositing an etch stop layer over the first dielectric layer and the graphite conductive feature;
depositing a second dielectric layer over the etch stop layer; and
forming a second conductive feature penetrating through the second dielectric layer, wherein the second conductive feature is over and electrically connected to the graphite conductive feature.

10. The method of claim 9 , wherein the graphite conductive feature has a lateral dimension smaller than about 12 nm.

11. The method of claim 9 , wherein the forming the dielectric spacer layer comprises a deposition process using a conformal deposition process.

12. The method of claim 9 further comprising forming an amorphous carbon layer over and contacting the graphite conductive feature, wherein the second conductive feature is over and contacts a top surface of the amorphous carbon layer.

13. The method of claim 9 further comprising forming an amorphous carbon layer, wherein the second conductive feature penetrates through the amorphous carbon layer to contact a crystalline inner portion of the graphite conductive feature.

14. The method of claim 13 , wherein the amorphous carbon layer further comprises fluorine.

15. A method comprising:
forming an integrated circuit;
forming a dual damascene structure comprising:
a metal line and a via, wherein the dual damascene structure comprises a barrier layer and a copper region over the barrier layer;

forming a graphite line electrically coupled between the via and the integrated circuit; and
forming a dielectric spacer layer encircling the graphite line, wherein at a time after the dielectric spacer layer is formed, a surface portion of the graphite line has been converted into an amorphous layer, and the dielectric spacer layer is deposited on the amorphous layer.

16. The method of claim 15 , wherein the graphite line has a top width and a bottom width, wherein the bottom width is greater than the top width.

17. The method of claim 12 , wherein the amorphous carbon layer is formed by converting a surface layer of the graphite conductive feature to the amorphous carbon layer.

18. The method of claim 13 , wherein the forming the amorphous carbon layer comprises converting a surface layer of the graphite conductive feature to the amorphous carbon layer.

19. The method of claim 15 , wherein the dielectric spacer layer is deposited as a conformal layer comprising a horizontal portion overlapping the graphite line, and vertical portions on sidewalls of the graphite line.

20. The method of claim 12 , wherein the graphite conductive feature has a top width and a bottom width, with the bottom width being greater than the top width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Chang Chih-Yi
• Chan Wei Hsiang
• Chi Chih-Chien
• Lin Chi-Feng
• Su Hung-Wen

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/267

  using plasmas · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title