Coreless electronic substrates having embedded inductors

Patent metadata

Field	Value
Publication number	US-12334242-B2
Application number	US-202117199005-A
Country	US
Kind code	B2
Filing date	Mar 11, 2021
Priority date	Mar 11, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

First claim

What is claimed is:

1. An apparatus, comprising:
a first magnetic element on only a first dielectric material layer;
a second dielectric material layer over, and in contact with, the first magnetic element and the first dielectric material layer;
a second magnetic element over the first magnetic element, and in contact with a surface of the second dielectric material layer, the second dielectric material layer having a non-zero thickness between the first magnetic element and the second magnetic element; and
an inductor coil over the first magnetic element, in contact with the surface of the second dielectric material layer, and partially embedded within the second magnetic element, wherein the second dielectric material layer has the non-zero thickness between the first magnetic element and the inductor coil.

2. The apparatus of claim 1 , further comprising a third dielectric material layer over the second magnetic element and over the second dielectric material layer, wherein the inductor coil is coplanar with a first conductive trace adjacent to the second magnetic element, wherein the first conductive trace is in contact with a first conductive via, and wherein the first conductive trace and the first conductive via extend through a thickness of the third dielectric material layer.

3. The apparatus of claim 1 , wherein the inductor coil is encapsulated by the second magnetic element and the second magnetic element is encapsulated by the second dielectric material layer.

4. The apparatus of claim 1 , wherein the first magnetic element is encapsulated by the second dielectric material layer.

5. The apparatus of claim 1 , further comprising a barrier dielectric material layer, and wherein the second dielectric material layer is over the barrier dielectric material layer.

6. The apparatus of claim 1 , further comprising:
at least one integrated circuit device coupled to the inductor coil through conductive routes comprising a first trace and a first via embedded within the second dielectric material layer, wherein a surface of the via is coplanar with the surface of the second dielectric material layer.

7. The apparatus of claim 6 , wherein first and second ends of the inductor coil are electrically coupled to two conductive routes.

8. The apparatus of claim 6 , further comprising an electronic board, wherein the apparatus is attached to the electronic board.

9. A coreless package substrate, comprising:
a first metallization level on a first side of the coreless package substrate, the first metallization level within a first layer of organic dielectric material and comprising a first conductive trace in direct contact with a first conductive via;
a body of magnetic material embedded within a second layer of organic dielectric material, and extending over only the first layer of organic dielectric material, wherein a top surface of the second layer of organic dielectric material extends over the body of magnetic material and is in contact with the first layer of organic dielectric material within an area beyond the body of magnetic material;
a second conductive trace adjacent to the body of magnetic material, in contact with the first conductive via, and embedded within the second layer of organic dielectric material;
a second conductive via in contact with the second conductive trace and embedded within the second layer of organic dielectric material, wherein a top surface of the second conductive via is coplanar with the top surface of the second layer of organic dielectric material;
a second metallization level on a second side of the coreless package substrate, the second metallization level within a third layer of organic dielectric material and comprising an inductor coil over the magnetic material, wherein the inductor coil is in direct contact with the second layer of organic dielectric material and spaced apart from the body of magnetic material by a non-zero thickness of the second layer of organic dielectric material.

10. The coreless package substrate of claim 9 , wherein the inductor coil is in direct contact with the second layer of organic dielectric material.

11. The coreless package substrate of claim 9 , further comprising a second body of magnetic material embedded within the third layer of organic dielectric material, wherein a top surface of the third layer of organic dielectric material extends over the second body of magnetic material, and a top surface of the second body of magnetic material extends over a top surface of the inductor coil.

12. The coreless package substrate of claim 11 , wherein the second metallization level comprises a third conductive trace in contact with the second conductive via.

13. The coreless package substrate of claim 12 , wherein a portion of the third layer of organic dielectric material is between the third conductive trace and the second body of magnetic material.

14. The coreless package substrate of claim 12 , wherein the second metallization level comprises a third conductive via in contact with the third conductive trace, and wherein a top surface of the third layer of organic polymeric dielectric material is adjacent to, but not over, the third conductive via.

Assignees

• Intel Corp

Inventors

• Ganesan Sanka
• Chavali Sri Chaitra Jyotsna
• Sankman Robert L
• Augustine Anne
• Radhakrishnan Kaladhar

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title