Link evaluation for a memory device

Patent metadata

Field	Value
Publication number	US-12334172-B2
Application number	US-202318112830-A
Country	US
Kind code	B2
Filing date	Feb 22, 2023
Priority date	Dec 19, 2019
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

First claim

What is claimed is:

1. A method, comprising:
sampling, at a first device, a first signaling received via a channel based at least in part on a first reference point within a time domain and a voltage domain to obtain data associated with the first signaling, wherein the first reference point is at a first sampling time within a sample period;
sampling, at the first device, a second signaling received via the channel and associated with a first sequence of logic values based at least in part on a second reference point within the time domain and the voltage domain to obtain a second sequence of logic values, wherein the second reference point is at a second sampling time within the sample period; and
transmitting, by the first device, a third signaling based at least in part on the second sequence of logic values and the first sequence of logic values.

2. The method of claim 1 , further comprising:
determining a match between the second sequence of logic values and the first sequence of logic values; and
determining, based at least in part on the match, that a margin of error for the channel is greater than or equal to a difference between the second reference point and the first reference point.

3. The method of claim 1 , further comprising:
determining a mismatch between the second sequence of logic values and the first sequence of logic values; and
determining, based at least in part on the mismatch, that a margin of error for the channel is less than a difference between the second reference point and the first reference point.

4. The method of claim 1 , further comprising:
identifying the second signaling as associated with the first sequence of logic values based at least in part on a timing relationship between a command received by the first device and the second signaling being received.

5. The method of claim 1 , wherein the second reference point is at a different time within the time domain than the first reference point.

6. The method of claim 1 , wherein the second reference point is at a different voltage within the voltage domain than the first reference point.

7. The method of claim 1 , further comprising:
receiving, from a second device before determining the second sequence of logic values, an indication of the first sequence of logic values.

8. The method of claim 1 , further comprising:
sampling the second signaling based at least in part on the first reference point to obtain the first sequence of logic values.

9. The method of claim 1 , further comprising:
sampling the second signaling based at least in part on a third reference point in the time domain and the voltage domain to obtain a third sequence of logic values, wherein the third signaling is based at least in part on a comparison of the third sequence to the first sequence of logic values.

10. The method of claim 9 , wherein sampling the second signaling based at least in part on the third reference point occurs after sampling the second signaling based at least in part on the second reference point.

11. The method of claim 9 , wherein sampling the second signaling based at least in part on the third reference point occurs concurrently with sampling the second signaling based at least in part on the second reference point.

12. The method of claim 1 , further comprising:
adjusting a time or voltage reference used by a sampler included in the first device, wherein the adjusting is after sampling the first signaling and before sampling the second signaling, and wherein the second reference point corresponds to the adjusted time or the adjusted voltage reference.

13. The method of claim 1 , further comprising:
activating a second sampler included in the first device after sampling the first signaling, wherein a first sampler included in the first device is operable to use the first reference point and the second sampler is operable to use the second reference point.

14. The method of claim 1 , further comprising:
calibrating a sampler included in the memory first device based at least in part on determining that a margin of error for a channel operable to exchange data with the first device is deficient, wherein the third signaling comprises an indication of the calibration.

15. An apparatus, comprising:
a channel operable to exchange data between an array of memory cells and a second device for the apparatus;
one or more samplers coupled with the channel and operable to determine logic values based at least in part on first signaling received via the channel, wherein at least one of the one or more samplers is operable to use a first reference point in a time domain and in a voltage domain to obtain data associated with the first signaling, and wherein the first reference point is at a first sampling time within a sample period; and
a controller operable to cause the apparatus to:
determine, using the one or more samplers, a second sequence of logic values based at least in part on second signaling received via the channel and a second reference point in the time domain and the voltage domain, wherein the second signaling comprises a first sequence of logic values, and wherein the second reference point is at a second sampling time within the sample period; and
transmit feedback to the second device based at least in part on the second sequence of logic values and the first sequence of logic values.

16. The apparatus of claim 15 , wherein the one or more samplers comprise:
a first sampler operable to determine logic values using the first reference point; and
a second sampler operable to determine logic values using the second reference point.

17. The apparatus of claim 15 , wherein:
the second reference point is at a different time within the time domain than the first reference point; and
the second reference point is at a different voltage in the voltage domain than the first reference point.

18. The apparatus of claim 15 , wherein the controller is further operable to cause the apparatus to:
determine, using the one or more samplers, a third sequence of logic values based at least in part on the second signaling and a third reference point in the time domain and the voltage domain, wherein the feedback is based at least in part on a comparison of the third sequence to the first sequence of logic values.

19. The apparatus of claim 15 , wherein the controller is further operable to cause the apparatus to:
adjust a time or voltage reference used by the one or more samplers, wherein the time or voltage reference is adjusted after sampling the first signaling and before sampling the second signaling, and wherein the second reference point corresponds to the adjusted time or the adjusted voltage reference.

20. A non-transitory computer-readable medium storing code, the code comprising instructions executable by an electronic device to:
sample, at a first device, a first signaling based at least in part on a first reference point within a time domain and a voltage domain to obtain data associated with the first signaling, wherein the first reference point is at a first sampling time within a sample period;
sample, at the first device, a second signaling associated with a first sequence of logic values based at least in part on a second reference point within the time domain and the voltage domain to obtain a second sequence of logic values, wherein the second reference point is at a second sampling time within the sample period; and
transmit, by the first device, a third signaling based at least in par

Assignees

• Micron Technology Inc

Inventors

• Balb Markus
• Hein Thomas
• Hoenigschmid Heinz

Classifications

• G11C29/023 Primary

  in clock generator or timing circuitry · CPC title

• G11C29/50012 Primary

  of timing · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title