Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit

Patent metadata

Field	Value
Publication number	US-9960902-B1
Application number	US-201615380653-A
Country	US
Kind code	B1
Filing date	Dec 15, 2016
Priority date	Dec 15, 2016
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

First claim

What is claimed is:

1. A method of clock and data recovery in a receiver, comprising:
generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal by a clock manager circuit;
adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples;
adjusting, using the clock manager circuit relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and
reverting, using the clock manager circuit, the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

2. The method of claim 1 , wherein the first phase difference is substantially ninety degrees.

3. The method of claim 1 , wherein the second phase difference is substantially forty-five degrees.

4. The method of claim 1 , wherein the second phase difference is larger than a transition jitter width of the received signal.

5. The method of claim 1 , wherein the CDR circuit includes a bang-bang phase detector, and wherein the step of adjusting the phase of the sampling clock comprises operating on a current data sample, a current crossing sample, and a next data sample at the bang-bang phase detector.

6. The method of claim 1 , wherein the threshold time period is at least as long as a lock period of the CDR circuit.

7. The method of claim 1 , further comprising:
repeating the steps of adjusting and reverting at least one additional time.

8. A receiver, comprising:
sampling circuitry configured to generate data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal;
a clock and data recovery (CDR) circuit configured to adjust a phase of the sampling clock signal based on the data samples and the crossing samples; and
a clock manager circuit configured to adjust a relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees, and revert the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

9. The receiver of claim 8 , wherein the first phase difference is substantially ninety degrees.

10. The receiver of claim 8 , wherein the second phase difference is substantially forty-five degrees.

11. The receiver of claim 8 , wherein the second phase difference is larger than a transition jitter width of the received signal.

12. The receiver of claim 8 , wherein the CDR circuit includes a bang-bang phase detector, and wherein the bang-bang phase detector is configured to adjust the phase of the sampling clock comprises operating on a current data sample, a current crossing sample, and a next data sample at the bang-bang phase detector.

13. The receiver of claim 8 , wherein the threshold time period is at least as long as a lock period of the CDR circuit.

14. The receiver of claim 8 , wherein the clock manager circuit is configured to adjust and revert the relative phase a plurality of times.

15. An integrated circuit (IC), comprising:
a serializer/deserializer (SerDes) circuit coupled to a transmission channel; and
a receiver, disposed in the SerDes circuit, configured to obtain a received signal from the transmission channel, the receiver including:
sampling circuitry configured to generate data samples and crossing samples of the received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal;
a clock and data recovery (CDR) circuit configured to adjust a phase of the sampling clock signal based on the data samples and the crossing samples; and
a clock manager circuit configured to adjust a relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees, and revert the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

16. The IC of claim 15 , wherein the first phase difference is substantially ninety degrees.

17. The IC of claim 15 , wherein the second phase difference is substantially forty-five degrees.

18. The IC of claim 15 , wherein the second phase difference is larger than a transition jitter width of the received signal.

19. The IC of claim 15 , wherein the CDR circuit includes a bang-bang phase detector, and wherein the bang-bang phase detector is configured to adjust the phase of the sampling clock comprises operating on a current data sample, a current crossing sample, and a next data sample at the bang-bang phase detector.

20. The IC of claim 15 , wherein the threshold time period is at least as long as a lock period of the CDR circuit.

Assignees

• Xilinx Inc

Inventors

• Lin Winson
• Xu Yu
• Leung Caleb S
• Wong Alan C
• Borrelli Christopher J
• Frans Yohan
• Chang Kun-Yung

Classifications

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L1/205

  jitter monitoring · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/033

  using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title