Digital Verify Failbit Count (VFC) circuit

Patent metadata

Field	Value
Publication number	US-12334162-B2
Application number	US-202218091645-A
Country	US
Kind code	B2
Filing date	Dec 30, 2022
Priority date	Dec 26, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A failbit counting method includes controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format. Each of the one or more verification bits is a fail bit or a pass bit. The count result in unary format is stored in the counter. The method further includes controlling the counter to transcode the count result stored in the counter from unary format to binary format.

First claim

What is claimed is:

1. A failbit counting method comprising:
controlling a counter of a verify failbit count (VFC) circuit to count fail bits in a bit group including one or more verification bits, received at an input of the counter, to obtain a count result in unary format, each of the one or more verification bits being a fail bit or a pass bit, the counter including a plurality of counter stages coupled one after another, the plurality of counter stages including a sense stage configured to receive the bit group and a plurality of storage stages, and the count result in unary format being stored in the plurality of storage stages of the counter; and
controlling the counter to transcode the count result stored in the counter from unary format to binary format.

2. The failbit counting method according to claim 1 , wherein:
controlling the counter to transcode the count result stored in the counter from unary format to binary format includes controlling the counter stages to toggle a storage state of at least one counter stage of the counter stages.

3. The failbit counting method according to claim 2 , wherein:
the plurality of storage stages include N storage stages, N being an integer greater than two; and
controlling the counter to transcode the count result stored in the counter from unary format to binary format includes:
determining whether each of the sense stage and the N storage stages stores a fail bit.

4. The failbit counting method according to claim 3 , wherein controlling the counter to transcode the count result stored in the counter from unary format to binary format further includes:
in response to determining that each of the sense stage and the N storage stages stores a fail bit, toggling the storage state of an N-th storage stage.

5. The failbit counting method according to claim 4 , wherein:
determining whether each of the sense stage and the N storage stages stores a fail bit includes determining whether each of the sense stage and the N storage stages stores logic 1; and
toggling the storage state of the N-th storage stage includes resetting the N-th storage to store logic 0.

6. The failbit counting method according to claim 4 , wherein controlling the counter to transcode the count result stored in the counter from unary format to binary format further includes:
in response to determining that each of the sense stage and the N storage stages stores a fail bit, toggling the storage state of the sense stage.

7. The failbit counting method according to claim 3 , wherein controlling the counter to transcode the count result stored in the counter from unary format to binary format further includes:
in response to determining that not each of the sense stage and the N storage stages stores a fail bit, determining whether each of the sense stage and a first storage stage to an (N−1)-th storage stage stores a fail bit.

8. The failbit counting method according to claim 7 , wherein controlling the counter to transcode the count result stored in the counter from unary format to binary format further includes:
in response to determining that each of the sense stage and the first storage stage to the (N−1)-th storage stage stores a fail bit, toggling the storage state of the first storage stage.

9. The failbit counting method according to claim 3 , wherein controlling the counter to transcode the count result stored in the counter from unary format to binary format further includes:
controlling the sense stage to be in a state representing that the sense stage stores a fail bit.

10. The failbit counting method according to claim 2 , wherein:
each of the plurality of counter stages includes a counter latch; and
controlling the counter stages to toggle the storage state of the at least one counter stage includes providing pulsed control signals to the counter stages to toggle a storage state of the counter latch of the at least one counter stage.

11. The failbit counting method according to claim 10 , wherein:
each of the counter stages further includes:
a first transistor coupled between a first terminal of the counter latch and a ground;
a second transistor coupled between a second terminal of the counter latch and the ground; and
a transistor string coupled between the second terminal of the counter latch and a power supply; and

providing the pulsed control signals to the counter stages to toggle the storage state of the counter latch of the at least one counter stage includes providing each of the pulsed control signals to one of a gate of the first transistor, a gate of the second transistor, and a gate of a transistor in the transistor string of the at least one counter stage.

12. A memory device comprising:
a memory cell array;
a verify failbit count (VFC) circuit coupled to the memory cell array and including a counter, the counter including a plurality of counter stages coupled one after another, and the plurality of counter stages including a sense stage and a plurality of storage stages; and
a control logic coupled to the VFC circuit and configured to:
control the counter to count fail bits in a bit group including one or more verification bits, received at an input of the sense stage of the counter, to obtain a count result in unary format, each of the one or more verification bits being a fail bit or a pass bit, and the count result in unary format being stored in the plurality of storage stages of the counter; and
control the counter to transcode the count result stored in the counter from unary format to binary format.

13. The memory device according to claim 12 , wherein the controller is further configured to:
control the counter stages to toggle a storage state of at least one counter stage of the counter stages.

14. The memory device according to claim 13 , wherein:
the plurality of storage stages include N storage stages, N being an integer greater than two; and
the controller is further configured to determine whether each of the sense stage and the N storage stages stores a fail bit.

15. The memory device according to claim 14 , wherein the controller is further configured to:
in response to determining that each of the sense stage and the N storage stages stores a fail bit, control an N-th storage stage to toggle the storage stage.

16. The memory device according to claim 15 , wherein the controller is further configured to:
determine whether each of the sense stage and the N storage stages stores logic 1; and
reset the N-th storage to store logic 0.

17. The memory device according to claim 15 , wherein the controller is further configured to:
in response to determining that each of the sense stage and the N storage stages stores a fail bit, toggle the storage state of the sense stage.

18. The memory device according to claim 13 , wherein:
each of the plurality of counter stages includes a counter latch; and
the controller is further configured to provide pulsed control signals to the counter stages to toggle a storage state of the counter latch of the at least one counter stage.

19. The memory device according to claim 18 , wherein:
each of the counter stages further includes:
a first transistor coupled between a first terminal of the counter latch and a ground;
a second transistor coupled between a second terminal of the counter latch and the ground; and
a transistor string coupled between the second terminal of the counter latch and a power supply; and

the controller is further configured to provide each of the pulsed control signal

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Teng
• Kuriyama Masao

Classifications

• G11C29/20

  using counters or linear-feedback shift registers [LFSR] · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/56012

  Timing aspects, clock generation, synchronisation · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title