Phase change memory programming current leakage reduction

Patent metadata

Field	Value
Publication number	US-12329045-B2
Application number	US-202117543957-A
Country	US
Kind code	B2
Filing date	Dec 7, 2021
Priority date	Dec 7, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a ‘horizontal’ portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a dielectric layer;
a bottom heater within the dielectric layer;
a phase change memory stack comprising a bottom projection liner electrode upon the dielectric layer and upon the bottom heater, a phase change memory material upon the bottom projection liner electrode, a top electrode upon the phase change memory material, an encapsulation column that extends from a top surface of the top electrode to a top surface of the dielectric layer, and an airgap within the encapsulation column.

2. The semiconductor device of claim 1 , wherein the bottom projection liner electrode comprises a top-down view horizontal portion and a top-down view vertical portion that is orthogonal to the top-down view horizontal portion.

3. The semiconductor device of claim 2 , wherein the exposed portion of the top surface of the dielectric layer is diagonally located between the top-down view horizontal portion and the top-down view vertical portion of the bottom projection liner electrode.

4. The semiconductor device of claim 3 , wherein a top of the airgap is above a top surface of the top electrode.

5. The semiconductor device of claim 4 , wherein a bottom of the airgap is between a top surface of the dielectric layer and a top surface of the phase change material.

6. The semiconductor device of claim 5 , further comprising: a top contact directly upon the top electrode.

7. The semiconductor device of claim 6 , wherein the top contact is vertically aligned with the bottom projection liner electrode.

8. A semiconductor device comprising:
a dielectric layer;
a bottom heater within the dielectric layer;
a phase change memory stack comprising a bottom projection liner electrode upon the dielectric layer and upon the bottom heater, the bottom projection liner electrode comprises a top-down view horizontal portion and a top-down view vertical portion that is orthogonal to the top-down view horizontal portion, a phase change memory material upon the bottom projection liner electrode, a top electrode upon the phase change memory material, a first pair of encapsulation columns that are diagonally located between the top-down view vertical portion and the top-down view horizontal portion of the bottom projection liner electrode, and a airgap within each of the first pair of encapsulation columns.

9. The semiconductor device of claim 8 , wherein the phase change memory stack further comprises: a second pair of encapsulation columns diagonally located between the top-down view vertical portion and the top-down view horizontal portion of the bottom projection liner electrode.

10. The semiconductor device of claim 9 , wherein a top of each airgap is above a top surface of the top electrode.

11. The semiconductor device of claim 10 , wherein a bottom of each of airgap is between a top surface of the dielectric layer and a top surface of the phase change material.

12. The semiconductor device of claim 11 , further comprising: a top contact directly upon the top electrode.

13. The semiconductor device of claim 12 , wherein the top contact is vertically aligned with the bottom projection liner electrode.

14. A semiconductor device fabrication method comprising:
forming a heater within a dielectric layer;
forming a bottom projection liner electrode upon the heater and upon the dielectric layer;
forming a phase change memory upon the bottom projection liner electrode and upon the dielectric layer;
forming a top electrode upon the phase change memory;
forming an airgap opening entirely through the top electrode and entirely through the phase change memory to expose a portion of a top surface of the dielectric layer; and
forming an encapsulation layer within an inlet of the airgap opening to form an airgap within the airgap opening.

15. The semiconductor device fabrication method of claim 14 , wherein the bottom projection liner electrode comprises a top-down view horizontal portion and a top-down view vertical portion that is orthogonal to the top-down view horizontal portion.

16. The semiconductor device fabrication method of claim 15 , wherein the exposed portion of the top surface of the dielectric layer is diagonally located between the top-down view horizontal portion and the top-down view vertical portion of the bottom projection liner electrode.

17. The semiconductor device fabrication method of claim 16 , wherein a top of the airgap is above a top surface of the top electrode.

18. The semiconductor device fabrication method of claim 17 , wherein a bottom of the airgap is between a top surface of the dielectric layer and a top surface of the phase change material.

19. The semiconductor device fabrication method of claim 18 , further comprising: forming a top contact directly upon the top electrode.

20. The semiconductor device fabrication method of claim 19 , wherein the top contact is vertically aligned with the bottom projection liner electrode.

Assignees

• IBM

Inventors

• Ok Injo
• Seo Soon-Cheon
• Reznicek Alexander
• Kim Youngseok
• Philip Timothy Mathew

Classifications

• H10N70/8616

  Thermal insulation means · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/011

  Manufacture or treatment of multistable switching devices · CPC title

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title