Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-12328909-B2
Application number	US-202217720741-A
Country	US
Kind code	B2
Filing date	Apr 14, 2022
Priority date	Aug 10, 2021
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an active pattern on a substrate and extending in a first direction parallel to an upper surface of the substrate;
a pair of source/drain patterns on the active pattern and spaced apart from each other in the first direction;
a gate electrode that is between the pair of source/drain patterns, crosses the active pattern, and extends in a second direction parallel to the upper surface of the substrate that is different from the first direction; and
a plurality of channel patterns stacked on the active pattern between the pair of source/drain patterns and configured to electrically connect the pair of source/drain patterns to each other,
wherein each of the channel patterns is spaced apart from another one of the channel patterns in a third direction perpendicular to the upper surface of the substrate,
wherein each of the channel patterns comprises: a first portion between the gate electrode and at least one of the pair of source/drain patterns in a plan view; and a plurality of second portions in contact with the first portion and overlapped with the gate electrode in the third direction,
wherein each of the second portions is spaced apart from another one of the second portions in the second direction,
wherein a top surface of the active pattern comprises a first recessed portion that is between the pair of source/drain patterns in the first direction, in a plan view, and
wherein the first recessed portion is between two of the second portions in the second direction, in a plan view.

2. The semiconductor device of claim 1 , wherein a width of the first recessed portion in the second direction ranges from about five (5) nanometers (nm) to about forty (40) nm.

3. The semiconductor device of claim 1 , wherein a width of the first recessed portion in the first direction is equal to a width of the gate electrode in the first direction.

4. The semiconductor device of claim 1 , further comprising a device isolation layer on the substrate to define the active pattern,
wherein a bottom surface of the first recessed portion is located at a level lower than a top surface of the device isolation layer, where an upper layer of the substrate serves as a base reference layer.

5. The semiconductor device of claim 1 , wherein the top surface of the active pattern comprises a second recessed portion,
wherein the second recessed portion is between two of the second portions in the second direction, in a plan view, and
wherein the first recessed portion and the second recessed portion are spaced apart from each other in the second direction.

6. The semiconductor device of claim 1 , wherein a length of at least one of the second portions in the second direction is smaller than a length of the first portion in the second direction.

7. The semiconductor device of claim 1 , wherein a length of the first portion in the second direction is smaller than a length of each of the pair of source/drain patterns in the second direction.

8. The semiconductor device of claim 1 , further comprising a device isolation layer on the substrate to define the active pattern,
wherein a bottom surface of each of the pair of source/drain patterns is located at a level lower than a top surface of the device isolation layer, where an upper layer of the substrate serves as a base reference layer, and
wherein the gate electrode is on at least a portion of a top surface of the device isolation layer, at least a portion of a top surface of the active pattern, and at least a portion of top and bottom surfaces of each of the channel patterns.

9. The semiconductor device of claim 1 , wherein a width of a bottom surface of each of the pair of source/drain patterns in the second direction is greater than or equal to a width of a top surface of the active pattern in the second direction.

10. The semiconductor device of claim 1 , wherein the channel patterns comprises four or more channel patterns, the semiconductor device further comprising at least one first gate spacer and at least one second gate spacer on a side surface of the gate electrode,
wherein the at least one first gate spacer extends from a top surface of an uppermost one of the channel patterns in the third direction, and
wherein the at least one second gate spacer is between two or more of the channel patterns and contacts at least a portion of one of the channel patterns.

11. The semiconductor device of claim 10 , wherein the at least one second gate spacer overlaps the first portion of at least one of the channel patterns in the third direction.

12. The semiconductor device of claim 1 , wherein the gate electrode is on the top surface of the active pattern in the first recessed portion.

13. A semiconductor device, comprising:
an active pattern on a substrate and extending in a first direction parallel to an upper surface of the substrate;
a pair of source/drain patterns on the active pattern and spaced apart from each other in the first direction;
a gate electrode that is between the pair of source/drain patterns, crosses the active pattern, and extends in a second direction parallel to the upper surface of the substrate that is different from the first direction;
a channel patterns stacked on the active pattern between the pair of source/drain patterns and configured to electrically connect the pair of source/drain patterns to each other;
a gate insulating pattern between the gate electrode and the channel patterns;
a pair of gate spacers extending from a top surface of an uppermost one of the channel patterns in a third direction perpendicular to the upper surface of the substrate to be on at least a portion of opposing side surfaces of the gate electrode;
a gate capping pattern between the pair of gate spacers and on a top surface of the gate electrode;
an interlayer insulating layer on at least one top surface of one or more of the pair of source/drain patterns and at least one side surface of one or more of the pair of gate spacers;
a pair of active contacts penetrating the interlayer insulating layer and electrically connected to the pair of source/drain patterns, respectively; and
a gate contact penetrating the gate capping pattern and electrically connected to the gate electrode,
wherein each of the channel patterns is spaced apart from another one of the channel patterns in the third direction,
wherein each of the channel patterns comprises: a first portion between the gate electrode and at least one of the pair of source/drain patterns in a plan view; and a plurality of second portions in contact with the first portion and overlapped with the gate electrode in the third direction,
wherein each of the second portions is spaced apart from another one of the second portions in the second direction,
wherein a top surface of the active pattern comprises a first recessed portion that is between the pair of source/drain patterns in the first direction, in a plan view, and
wherein the first recessed portion is between two of the second portions in the second direction, in a plan view.

14. The semiconductor device of claim 13 , wherein the first portion contacts the at least one of the pair of source/drain patterns.

15. The semiconductor device of claim 13 , wherein each of the second portions is spaced apart from the at least one of the pair of source/drain patterns, with the first portion interposed therebetween.

16. The semiconductor device of claim 13 , wherein the first portion is overlapped with at least one of the pair of gate spacers in the third direction.

17. A

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myunggil
• Kim Dongwon
• Cho Keunhwi
• Ha Daewon

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title