Semiconductor device, power module and manufacturing method for the semiconductor device

Patent metadata

Field	Value
Publication number	US-12328884-B2
Application number	US-202318301793-A
Country	US
Kind code	B2
Filing date	Apr 17, 2023
Priority date	Aug 1, 2018
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A method for manufacturing a semiconductor device includes forming a trench on a first main surface of a conductive semiconductor substrate. The method includes laminating conductive layers, each of which is a first or a second conductive layer, along a surface normal direction of a side surface of the trench, while forming dielectric layers between a conductive layer closest to the side surface of the trench and the side surface of the trench, and between the corresponding conductive layers; and removing the first conductive layer and the dielectric layer, which are formed on a bottom portion of the trench, to electrically connect the second conductive layer to the semiconductor substrate at the bottom portion of the trench. After a portion of the first main surface, the portion being outside of the trench, is covered with an insulating protective film, the first conductive layer and the dielectric layer are removed.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a trench on a first main surface of a conductive semiconductor substrate;
laminating a plurality of conductive layers, each of which is either a first conductive layer or a second conductive layer, on one another along a side surface of the trench in a direction that is normal to the side surface of the trench;
forming dielectric layers (i) between a conductive layer closest to the side surface of the trench among the plurality of conductive layers and the side surface of the trench, and (ii) between the plurality of corresponding conductive layers;
removing the first conductive layer formed on a bottom portion of the trench and one of the dielectric layers that is (i) adjacent to the first conductive layer and (ii) formed on the bottom portion of the trench, such that the second conductive layer is electrically connected to the conductive semiconductor substrate at the bottom portion of the trench;
forming a first electrode, physically connected to the first conductive layer, outside the trench, wherein the first conductive layer includes
(i) one first conductive layer, and
(ii) another first conductive layer, the first electrode extending only through the one first conductive layer, of the first conductive layer, in a contact hole outside the trench in plan view; and

forming a second electrode, electrically connected to the second conductive layer via the conductive semiconductor substrate, on a second main surface of the conductive semiconductor substrate,
wherein the first conductive layer is electrically insulated from the conductive semiconductor substrate, and
wherein a portion of the first main surface outside the trench is covered with an insulating protective film, prior to removal of the first conductive layer formed on the bottom portion of the trench and the one of the dielectric layers that is (i) adjacent to the first conductive layer and (ii) formed on the bottom portion of the trench.

2. The method for manufacturing a semiconductor device according to claim 1 , wherein the insulating protective film is formed into a shape in which an end portion protrudes inward from the side surface of the trench.

3. The method for manufacturing a semiconductor device according to claim 1 , wherein an entirety of the conductive semiconductor substrate is conductive.

4. The method for manufacturing a semiconductor device according to claim 1 , wherein the second electrode is formed such that the conductive semiconductor substrate is disposed between the second electrode and the second conductive layer.

5. The method for manufacturing a semiconductor device according to claim 4 , wherein the second electrode and the conductive semiconductor substrate extend across the bottom surface of the trench.

Assignees

• Nissan Motor
• Renault Sas

Inventors

• Marui Toshiharu
• Hayashi Tetsuya
• Numakura Keiichiro
• Ni Wei
• Tanaka Ryota

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/047

  of conductor-insulator-semiconductor capacitors, e.g. trench capacitors · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10D1/665 Primary

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title