Massive parallel assembly method

Patent metadata

Field	Value
Publication number	US-12327751-B2
Application number	US-202217842430-A
Country	US
Kind code	B2
Filing date	Jun 16, 2022
Priority date	Dec 16, 2019
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A method for manufacturing a device is provided. The method comprises providing a first carrier having attached thereto a plurality of chips by means of an adhesive layer of the first carrier, a first surface of the plurality of chips being attached to the first carrier. Further, the method comprises selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by means of a structured adhesive layer of the conveyor layer. Further, the method comprises selectively releasing the subset of the plurality of chips from the first carrier by means of debonding corresponding sections of the adhesive layer of the first carrier. Further, the method comprises attaching the first surface of the subset of the plurality of chips to a substrate of the device.

First claim

What is claimed is:

1. A method for manufacturing a device, the method comprising:
providing a first carrier having attached thereto a plurality of chips by way of an adhesive layer disposed on the first carrier, wherein a first surface of the plurality of chips is attached to the first carrier;
selectively attaching a second surface of a subset of the plurality of chips to a conveyor carrier by way of a structured adhesive layer disposed on the conveyor layer;
selectively releasing the subset of the plurality of chips from the first carrier by way of debonding at corresponding sections of the adhesive layer of the first carrier to which the subset of the plurality of chips are attached;
attaching the first surface of the subset of the plurality of chips to a substrate of the device; and
releasing the subset of the plurality of chips from the conveyor carrier by way of debonding corresponding sections of the structured adhesive layer of the conveyor carrier to which the subset of the plurality of chips are attached,
wherein at least one of selectively releasing the subset of the plurality of chips from the first carrier and releasing the subset of the plurality of chips from the conveyor carrier is performed by way of laser debonding, and
wherein the first carrier and the conveyor carrier are glass carriers.

2. The method according to claim 1 , wherein the plurality of chips is a two-dimensional array of chips.

3. The method according to claim 1 , wherein the subset of the plurality of chips is defined by a two-dimensional pattern.

4. The method according to claim 3 , wherein according to the two-dimensional pattern, at least every second or third chip in a row direction and/or at least every second or third chip in a column direction is selected from the two-dimensional array of chips, to obtain the subset of chips.

5. The method according to claim 3 further comprising:
providing the conveyor carrier with an adhesive layer disposed thereon; and
structuring the adhesive layer of the conveyor carrier based on the two-dimensional pattern defining the subset of the chips, to obtain the structured adhesive laser of the conveyor layer.

6. The method according to claim 1 , wherein attaching the first surface of the subset of the plurality of chips to the substrate of the device comprises bonding the subset of the plurality of chips to the substrate of the device.

7. The method according to claim 1 , wherein the first surface of plurality of chips comprises a metallization layer.

8. The method according to claim 1 , wherein the first surface of the subset of the plurality of chips comprises a metallization layer having disposed thereon an AuSn solder layer stack,
wherein attaching the first surface of the subset of the plurality of chips to the substrate of the device comprises soldering the subset of the plurality of chips to the substrate of the device at a temperature of at least 280° C.

9. The method according to claim 1 , wherein the first carrier is a handling carrier.

10. The method according to claim 1 , wherein the first carrier is a donor carrier, and wherein providing the first carrier comprises:
providing a handling carrier having attached thereto the plurality of chips by way of an adhesive layer of the handling carrier, the second surface of the plurality of chips being attached to the handling carrier;
attaching the first surface of the plurality of chips or a subset of the plurality of chips to the donor carrier by way of the adhesive layer of the donor carrier; and
releasing the plurality of chips or the subset of the plurality of chips from the handling carrier by way of laser debonding at least corresponding sections of the adhesive layer of the handling carrier.

11. The method according to claim 10 , wherein providing the first carrier that is the donor carrier further comprises:
providing a metallization layer on the first surface of the devices prior to attaching the first surface of the plurality of chips to the donor carrier; or
providing a metallization layer on the first surface of the devices prior to attaching the first surface of the plurality of chips to the donor carrier and providing an AuSn solder layer stack on the metallization layer.

12. The method according to claim 9 , wherein providing the first carrier which is the handling carrier comprises:
providing a substrate having formed thereon the plurality of chips;
attaching the substrate with the plurality of chips to the handling carrier by way of an adhesive layer, the plurality of chips facing the carrier; and
separating the plurality of chips from the substrate.

13. The method according to claim 1 , wherein the plurality of chips are a first plurality of chips, and wherein the method further comprises:
providing a second carrier having attached thereto a second plurality of chips by way of an adhesive layer of the second carrier, a first surface of the second plurality of chips being attached to the second carrier;
selectively attaching a second surface of a subset of the second plurality of chips to a second conveyor carrier by way of a structured adhesive layer of the second conveyor layer;
selectively releasing the subset of the second plurality of chips from the second carrier by way of laser debonding corresponding sections of the adhesive layer of the second carrier;
attaching the first surface of the subset of the second plurality of chips to the substrate of the device; and
releasing the subset of the second plurality of chips from the second conveyor carrier by way of laser debonding at least corresponding sections of the structured adhesive layer of the second conveyor carrier.

14. The method according to claim 13 , wherein the subset of the first plurality of chips and the subset of the second plurality of chips are arranged in an interleaved manner with respect to each other on the substrate of the device.

15. The method according to claim 13 , wherein the first surface of the subset of the first plurality of chips and the first surface of the subset of the second plurality of chips comprises a metallization layer having disposed thereon an AuSn solder layer stack,
wherein attaching the first surface of the subset of the first plurality of chips to the substrate of the device comprises soldering the first subset of the first plurality of chips to the substrate of the device at a temperature between 280° C. and 350° C.;
wherein attaching the first surface of the subset of the second plurality of chips to the substrate of the device comprises soldering the subset of the second plurality of chips to the substrate of the device at a temperature between 280° C. and 350° C.; and
wherein the first plurality of chips are soldered to the substrate of the device prior to attaching the first surface of the subset of the second plurality of chips to the substrate of the device.

16. The method according to claim 1 , wherein the plurality of chips are at least one of semiconductor chips, optical filters, ferromagnets, high-K dielectrics, tilting mirrors, micro lenses, laser diodes, photodetectors and light emitting diodes.

17. The method according to claim 1 , wherein the device is a display or a part of a display, or wherein the device is an optical module or part of an optical module, or wherein the device is a power regulator or switches.

18. The method according to claim 1 , including:
attaching a first surface of a subset of a second plurality of chips to the substrate of the device by soldering the subset of the second plurality of chips

Assignees

• Huawei Tech Duesseldorf Gmbh
• Fraunhofer Ges Forschung

Inventors

• Oppermann Hans-Hermann
• Zoschke Kai
• Manier Charles-Alix

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/59

  Bond pads specially adapted therefor · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07336

  Soldering or alloying · CPC title