Drift detection in timing signal forwarded from memory controller to memory device

Patent metadata

Field	Value
Publication number	US-12326751-B2
Application number	US-202418635817-A
Country	US
Kind code	B2
Filing date	Apr 15, 2024
Priority date	Oct 26, 2011
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

First claim

What is claimed is:

1. A memory device comprising:
a memory core to store data;
an interface circuit to receive, from a memory controller, a first timing signal having a first frequency, wherein the first timing signal is to be used to time a data transfer operation with the memory core;
a drift detection circuit that mimics a timing delay through a clock distribution circuit in the memory device where the clock distribution circuit uses the first timing signal for the data transfer operation, the drift detection circuit comprising a phase to digital converter to determine a phase delay between a second timing signal that is received from the memory controller and the second timing signal that is delayed by a plurality of different delay elements, and the drift detection circuit to generate a digital code that is indicative of the phase delay; and
a transmitter to output information including the digital code to the memory controller.

2. The memory device of claim 1 , wherein the second timing signal is different from the first timing signal.

3. The memory device of claim 2 , wherein the first timing signal has a first frequency and the second timing signal has a second frequency that is less than the first frequency.

4. The memory device of claim 1 , wherein the second timing signal is not used by the memory device for the data transfer operation between the memory core and the memory controller.

5. The memory device of claim 1 , wherein the interface circuit receives the second timing signal from the memory controller during a power down event or a calibration event of the memory device.

6. The memory device of claim 1 , wherein subsequent to the transmitter outputting the information to the memory controller, the interface circuit receives the first timing signal with a phase delay that has been adjusted by the memory controller based on the digital code outputted by the transmitter, and wherein the memory controller and the memory device perform the data transfer operation according to the first timing signal with the adjusted phase delay.

7. The memory device of claim 1 , wherein each delay element from the plurality of different delay elements delays the second timing signal by a phase amount representative of drift characteristics of a distinct portion of distribution of the first timing signal in the memory device to generate a third timing signal.

8. The memory device of claim 7 , wherein the phase to digital converter determines a plurality of instances of phase delay through the clock distribution circuit in a form of digital codes, each instance of phase delay determined based on a difference between the second timing signal and one of a plurality of third timing signals generated by the plurality of different delay elements, the difference indicative of the phase delay caused by the timing delay.

9. The memory device of claim 8 , wherein the phase to digital converter comprises:
a first phase mixer that adjusts a phase of the second timing signal by a first phase adjustment amount to generate a fourth timing signal;
a second phase mixer that adjusts a phase of the third timing signal by a second phase adjustment amount to generate a fifth timing signal;
a phase detector that determines whether the fourth timing signal and the fifth timing signal are substantially in phase; and
a control circuit that generates the digital code representative of a difference between the first phase adjustment amount and the second phase adjustment amount when the fourth timing signal and the fifth timing signal are substantially in phase.

10. The memory device of claim 1 , wherein the drift detection circuit comprises CMOS digital circuitry.

11. The memory device of claim 9 , wherein the drift detection circuit remains on during the data transfer operation between the memory device and the memory controller.

12. A method of operating a memory device including a memory core that stores data, the method comprising:
receiving from a memory controller a first timing signal having a first frequency, wherein the first timing signal is to be used to time a data transfer operation with the memory core;
mimicking a timing delay through a clock distribution circuit in the memory device where the clock distribution circuit uses the first timing signal for the data transfer operation to determine a phase delay between a second timing signal that is received from the memory controller and the second timing signal that is delayed by a plurality of different delay elements;
generating information including a digital code that is indicative of the phase delay occurring on the second timing signal in the memory device; and
outputting the information to the memory controller.

13. The method of claim 12 , wherein the second timing signal is different from the first timing signal.

14. The method of claim 13 , wherein the first timing signal has a first frequency and the second timing signal has a second frequency that is less than the first frequency.

15. The method of claim 12 , wherein the second timing signal is not used by the memory device for the data transfer operation between the memory core and the memory controller.

16. The method of claim 12 , wherein the second timing signal is received from the memory controller during a power down event or a calibration event of the memory device.

17. The method of claim 12 , further comprising:
receiving the first timing signal with a phase delay that has been adjusted by the memory controller based on the digital code subsequent to outputting the information to the memory controller, and
performing the data transfer operation with the memory controller according to the first timing signal with the adjusted phase delay.

18. The method of claim 12 , further comprising:
delaying the second timing signal using the plurality of different delay elements to generate a plurality of third timing signals that each correspond to a corresponding delay element from the plurality of different delay elements, each delay element delaying the second timing signal by a corresponding phase amount representative of drift characteristics of a distinct portion of the clock distribution circuit; and
determining a plurality of instances of phase delay through the clock distribution circuit in a form of digital codes, each instance of phase delay determined based on a difference between the second timing signal and one of the plurality of third timing signals, the difference indicative of the phase delay caused by timing drift.

19. The method of claim 18 , wherein determining the plurality of instances of the phase delay comprises:
adjusting a phase of the second timing signal by a first phase adjustment amount to generate a fourth timing signal;
adjusting a phase of one of the plurality of third timing signals by a second phase adjustment amount to generate a fifth timing signal;
determining whether the fourth timing signal and the fifth timing signal are substantially in phase; and
generating a digital code representative of a difference between the first phase adjustment amount and the second phase adjustment amount when the fourth timing signal and the fifth timing signal are in phase.

20. A memory device comprising:
a means for storing data;
a means for receiving, from a memory controller, a first timing signal having a first frequency, wherein the first timing signal is to be used to time a data transfer operation with the means for storing data;
a means for mimicking a timing delay through

Assignees

• Rambus Inc

Inventors

• Kim Jun
• Chau Pak Shing
• Richardson Wayne S

Classifications

• G06F13/1673

  using buffers · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• H04L7/10

  Arrangements for initial synchronisation · CPC title