Configurable microphone using internal clock changing

Patent metadata

Field	Value
Publication number	US-12325627-B2
Application number	US-202016773079-A
Country	US
Kind code	B2
Filing date	Jan 27, 2020
Priority date	Jan 27, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.

First claim

What is claimed is:

1. A method of operating a digital device, the method comprising:
in a first operational mode, converting an analog output of a microelectromechanical system (MEMS) into a first internal data stream having a first sampling rate derived from a clock frequency of an undivided clock signal and a first external data stream having the first sampling rate;
transitioning from the first operational mode to a second operational mode without restarting the MEMS;
in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream having the first sampling rate, wherein the second sampling rate is derived from a clock frequency of a divided clock signal;
inputting the undivided clock signal into a first input of a multiplexer;
inputting the undivided clock signal into a clock divider to generate the divided clock signal;
inputting the divided clock signal into a second input of the multiplexer; and
inputting a control signal to a control input of the multiplexer, the control signal indicating one of the first and second operational modes,
wherein, in the first operational mode, the multiplexer couples the first input of the multiplexer to an output of the multiplexer, wherein, in the second operational mode, the multiplexer couples the second input of the multiplexer to the output of the multiplexer, and wherein the output of the multiplexer provides the undivided clock signal in the first operational mode and provides the divided clock signal in the second operational mode.

2. The method of claim 1 , wherein the first external data stream and the second external data stream are provided at one or more output nodes.

3. The method of claim 1 , wherein performing a sampling rate conversion of the second internal data stream to generate a second external data stream comprises repeating samples in the second internal data stream.

4. The method of claim 1 , wherein converting the analog output of the MEMS comprises performing a sigma-delta analog-to-digital conversion on the analog output of the MEMS.

5. The method of claim 1 , wherein converting the analog output of the MEMS into the first internal data stream is performed by a signal processing circuit clocked at the first sampling rate, and wherein converting the analog output of the MEMS into the second internal data stream is performed by the signal processing circuit clocked at the second sampling rate.

6. The method of claim 5 , wherein the signal processing circuit comprises an analog-to-digital converter (ADC) and a digital filter.

7. The method of claim 6 , further comprising providing a first set of coefficients to the digital filter in the first operational mode and providing a second set of coefficients to the digital filter in the second operational mode.

8. The method of claim 6 , wherein the signal processing circuit further comprises a digital modulator.

9. The method of claim 1 , wherein the MEMS comprises a microphone.

10. A circuit comprising:
a clock divider having an input coupled to a clock signal input;
a multiplexer having a first input coupled to an output of the clock divider, a second input coupled to the clock signal input, a third input coupled to a control signal input, and an output, wherein the multiplexer is configured to couple either of the first input and the second input to the output of the multiplexer according to a state of the control signal input;
a signal processing circuit having an analog signal input, a clock input coupled to the output of the multiplexer, and a digital signal output comprising one or more output nodes; and
a frequency converter coupled between the digital signal output of the signal processing circuit and a data stream output, wherein a conversion factor of the frequency converter is determined according to the state of the control signal input,
wherein the signal processing circuit is configured to:
in a first operational mode, convert an analog output of a microelectromechanical system (MEMS) into a first internal data stream having a first sampling rate derived from a clock frequency of an undivided clock signal and a first external data stream having the first sampling rate;
transition from the first operational mode to a second operational mode without restarting the MEMS;
in the second operational mode, convert the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and perform a sampling rate conversion of the second internal data stream to generate a second external data stream having the first sampling rate, wherein the second sampling rate is derived from a clock frequency of a divided clock signal;
input the undivided clock signal into the first input of the multiplexer;
input the undivided clock signal into the clock divider to generate the divided clock signal;
input the divided clock signal into the second input of the multiplexer; and
input a control signal to a control input of the multiplexer, the control signal indicating one of the first and second operational modes,
wherein, in the first operational mode, the multiplexer couples the first input of the multiplexer to the output of the multiplexer, wherein, in the second operational mode, the multiplexer couples the second input of the multiplexer to the output of the multiplexer, and wherein the output of the multiplexer provides the undivided clock signal in the first operational mode and provides the divided clock signal in the second operational mode.

11. The circuit of claim 10 , wherein the first external data stream and the second external data stream are provided at one or more output nodes.

12. The circuit of claim 10 , wherein performing a sampling rate conversion of the second internal data stream to generate a second external data stream comprises repeating samples in the second internal data stream.

13. The circuit of claim 10 , wherein converting the analog output of the MEMS comprises performing a sigma-delta analog-to-digital conversion on the analog output of the MEMS.

14. The circuit of claim 10 , wherein converting the analog output of the MEMS into the first internal data stream is performed by the signal processing circuit clocked at the first sampling rate, and wherein converting the analog output of the MEMS into the second internal data stream is performed by the signal processing circuit clocked at the second sampling rate.

15. The circuit of claim 14 , wherein the signal processing circuit comprises an analog-to-digital converter (ADC) and a digital filter.

16. The circuit of claim 15 , wherein the signal processing circuit further comprises a digital modulator.

17. The circuit of claim 10 , wherein the MEMS comprises a microphone.

18. A microelectromechanical (MEMS) circuit in a single package comprising:
a control signal input, a clock signal input, and a data stream output for providing a constant rate single bit output stream at one or more output nodes;
a MEMS device; and
a signal processing circuit coupled to the MEMS device, to the control signal input, to the clock signal input, and the data stream output, wherein the signal processing circuit is configured to:
in a first operational mode, convert an analog output of the MEMS device into a first internal data stream having a first sampling rate derived from a clock f

Assignees

• Infineon Technologies Ag

Inventors

• Straeussnigg Dietmar
• Neumaier Daniel

Classifications

• H04R2201/003

  Mems transducers or their use · CPC title

• H04R19/04 Primary

  Microphones (H04R19/01 takes precedence) · CPC title

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/47

  using time-division multiplexing · CPC title

• H04R2203/00

  Details of circuits for transducers, loudspeakers or microphones covered by H04R3/00 but not provided for in any of its subgroups · CPC title