Microphone circuit assembly and system with speech recognition

Patent metadata

Field	Value
Publication number	US-9542933-B2
Application number	US-201313789847-A
Country	US
Kind code	B2
Filing date	Mar 8, 2013
Priority date	Mar 8, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.

First claim

The invention claimed is:

1. A method, comprising:
buffering audio samples received from a microphone,
performing speech recognition on the buffered audio samples using a locally-stored vocabulary as a reference, and
when the speech recognition identifies a recognized speech element, outputting a wake up signal indicating a match and outputting buffered audio signals corresponding to the recognized speech element,
wherein at least one of the buffering, the performing, and the outputting is performed at least in part by a processor.

2. The method of claim 1 , further comprising outputting the buffered audio signals received subsequent to the buffered audio signals that correspond to the recognized speech element.

3. The method of claim 2 , further comprising:
performing second speech recognition on the outputted buffered audio signals, both those corresponding to the recognized speech element and those received subsequent to the buffered audio signals that correspond to the recognized speech element,
wherein the second speech recognition is more sophisticated than the speech recognition performed using the locally-stored vocabulary.

4. The method of claim 1 , wherein outputting of buffered audio signals is prevented before the speech recognition identifies the recognized speech element.

5. The method of claim 1 , wherein the outputting of the buffered audio signals corresponding to the recognized speech element occurs after receiving an acknowledgment of the wake up signal.

6. The method of claim 1 , further comprising deactivating the performing speech recognition after the speech recognition identifies the recognized speech element, and outputting buffered audio signals received subsequent to the buffered audio signals that correspond to the recognized speech element.

7. The method of claim 1 , further comprising:
generating the audio samples from an input audio signal, wherein,
before the speech recognition identifies the recognized speech element, the generating occurs at a first sampling rate, and
after the speech recognition identifies the recognized speech element, the generating occurs at a second sampling rate higher than the first sampling rate.

8. The method of claim 1 , further comprising:
generating the audio samples from an input audio signal, wherein,
before the speech recognition identifies the recognized speech element, the samples have a first dynamic range, and
after the speech recognition identifies the recognized speech element, the samples have a second dynamic range higher than the first dynamic range.

9. A system, comprising:
a buffer to store samples representing an input audio signal,
a speech feature extractor having an input for samples from the buffer,
a speech vocabulary storing data representing a predetermined set of speech elements, and
a controller comprising a decision circuit to generate a wake up signal in response to a match between speech features output by the extractor and the stored speech elements, wherein the controller is configured to output a wake up signal indicating the match and to output samples received subsequent to the samples stored in the buffer corresponding to the match.

10. The system of claim 9 , further comprising a speech recognition system, responsive to the wake up signal, to transition from a low power mode to a high power mode and perform speech recognition on samples representing the input audio signal.

11. The system of claim 10 , wherein the speech vocabulary stores a fewer number of speech elements than can be recognized by the speech recognition system.

12. The system of claim 10 , wherein the speech recognition system is provided on an integrated circuit die separate from another integrated circuit die that includes the buffer, the speech feature extractor, the speech vocabulary and the controller.

13. The system of claim 10 , wherein the buffer, the speech feature extractor, the speech vocabulary, the controller, and the speech recognition system are provided on a common integrated circuit die.

14. The system of claim 9 , further comprising a data interface to output stored samples corresponding to the match.

15. The system of claim 9 , further comprising an analog-to-digital converter (ADC) to generate the samples, the ADC operative in at least:
a first power mode wherein the ADC generates samples at a first sample rate, and
a second power mode wherein the ADC generates samples at a second sample rate, higher than the first sample rate.

16. The system of claim 9 , further comprising an analog-to-digital converter (ADC) to generate the samples, the ADC operative in at least:
a first power mode wherein the ADC generates samples at a first dynamic range, and
a second power mode wherein the ADC generates samples at a second dynamic range, higher than the first dynamic range.

17. The system of claim 9 , wherein the buffer is a circular buffer having a capacity between 500 ms and 1 second of audio samples.

18. A non-transitory computer readable medium storing program instructions that, when executed by a processing device, causes the device to:
buffer input audio samples,
perform speech recognition on the buffered audio samples using a vocabulary as a reference, and
when the speech recognition identifies a recognized speech element, generating a wake up command indicating a match;
wherein the instructions further cause the device to output the wake up command and to output audio samples received subsequent to the buffered audio samples that correspond to the recognized speech element.

19. The medium of claim 18 , wherein the instructions further cause the device to:
responsive to the wake up command, instantiate a second speech recognition process by the device, the second speech recognition process operating on the buffered audio samples that correspond to the recognized speech element and audio samples that follow the audio samples that correspond to the recognized speech element,
wherein the second speech recognition process is more sophisticated than the speech recognition performed using the vocabulary.

20. The medium of claim 18 , wherein the instructions further cause the device to deactivate the performing speech recognition after the speech recognition identifies the recognized speech element.

21. The system of claim 9 , further comprising:
a microphone to capture the input audio signal,
a preamplifier coupled to the microphone, and
an analog to digital converter coupled to the preamplifier having an output in communication with the buffer.

22. The method of claim 1 , wherein the performing the speech recognition on the buffered audio samples includes identifying a target word or target phrase from the buffered audio samples, and wherein the recognized speech element includes the target word or target phrase.

23. The method of claim 3 , wherein the speech recognition performed using the locally-stored vocabulary is limited by one or more of a processor word length, a memory usage characteristic, or an FFT block size, and wherein the more sophisticated second speech recognition is less limited by a corresponding and respective one of the processor word length, memory usage characteristic, or FFT block size.

24. The method of claim 3 , wherein the speech recognition performed using the locally-stored vocabulary is performed by a processor circuit under a first power consumption constraint, and wherein the more sophistica

Assignees

• Analog Devices Global

Inventors

• Mortensen Mikael

Classifications

• G10L15/265

  Physics · mapped topic

• G10L15/08

  Speech classification or search · CPC title

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• H04R2225/43

  Signal processing in hearing aids to enhance the speech intelligibility · CPC title

• G10L15/22

  Procedures used during a speech recognition process, e.g. man-machine dialogue · CPC title