Display device having an emission layer

Patent metadata

Field	Value
Publication number	US-12324324-B2
Application number	US-202418739910-A
Country	US
Kind code	B2
Filing date	Jun 11, 2024
Priority date	Oct 11, 2016
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of pixels, each of the plurality of pixels comprising a pixel electrode and a plurality of transistors;
a conductive pattern disposed in a same layer as the pixel electrode;
a shielding part; and
a driving voltage line disposed in a same layer as the shielding part,
wherein the plurality of transistors of each of the plurality of pixels comprises:
a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region;
a second transistor including a second gate electrode, a second channel region overlapping the second gate electrode, a second drain region electrically connected to the first gate electrode, and a second source region opposing the second drain region with respect to the second channel region; and
a third transistor including a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region electrically connected to the first gate electrode and extending from the second drain region, and a third source region opposing the third drain region with respect to the third channel region,
wherein the driving voltage line overlaps the third channel region,
wherein the shielding part overlaps the second channel region,
wherein one of the pixel electrode and the conductive pattern overlaps the second channel region, and another one of the pixel electrode and the conductive pattern overlaps the third channel region, in a pixel of the plurality of pixels, and
wherein the second source region of the second transistor is extended from the first drain region of the first transistor.

2. The display device of claim 1 , wherein
the plurality of pixels comprises a first pixel and a second pixel,
in the first pixel, the pixel electrode overlaps the second channel region, and
in the second pixel, the conductive pattern overlaps the second channel region.

3. The display device of claim 1 , further comprising:
a first connector connected to the first gate electrode and disposed in a different conductive layer from the first gate electrode,
wherein the second drain region is electrically connected to the first gate electrode via the first connector.

4. The display device of claim 3 , wherein the shielding part is in a same conductive layer as the first connector, and separated from the first connector.

5. The display device of claim 3 , wherein the display panel further comprises:
a substrate;
a first insulating layer;
a storage line;
a second insulating layer; and
a third insulating layer,
wherein an active pattern including the first channel, the second channel, and the third channel is disposed on the substrate,
wherein the first gate electrode is disposed on the active pattern,
wherein the first insulating layer is disposed on the first gate electrode,
wherein the storage line is disposed on the first insulating layer,
wherein the second insulating layer is disposed on the storage line,
wherein the driving voltage line is disposed on the second insulating layer,
wherein the third insulating layer is disposed on the driving voltage line, and
wherein the pixel electrode and the conductive pattern are disposed on the third insulating layer.

6. The display device of claim 5 , wherein the storage line comprises an expansion overlapping the first gate electrode.

7. The display device of claim 1 , wherein the shielding part is configured to transmit an initialization voltage line.

8. The display device of claim 7 , further comprising
an initialization voltage line for transmitting the initialization voltage,
wherein the shielding part is electrically connected to the initialization voltage.

9. The display device of claim 1 , wherein the shielding part comprises a same material as the driving voltage line.

10. The display device of claim 1 , further comprising:
a scan line disposed in a same conductive layer as the first gate electrode,
wherein the second gate electrode is a portion of the scan line.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jun Won
• Kim Dong Soo
• Bang Hyun-Chol
• Pyon Chang Soo
• Lee Ji-Eun

Classifications

• H10K59/805

  Electrodes · CPC title

• H10K59/126 Primary

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/8792

  comprising light absorbing layers, e.g. black layers · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title