Display device having an emission layer

Patent metadata

Field	Value
Publication number	US-10658448-B2
Application number	US-201916421885-A
Country	US
Kind code	B2
Filing date	May 24, 2019
Priority date	Oct 11, 2016
Publication date	May 19, 2020
Grant date	May 19, 2020

Abstract

A display device includes signal lines and pixels connected thereto. A first pixel includes a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode, a first source region, and a second drain region facing the first source region, with the first channel region interposed between the first source region and the second drain region. A third transistor includes a third gate electrode, a third channel region overlapping the third gate electrode, a third drain region connected to the first gate electrode, and a third source region facing the third drain region with the third channel region interposed between the third source region and the third drain region. A shielding part overlaps a boundary between the third source region and the third channel region and does not overlap a boundary between the third drain region and the third channel region.

First claim

What is claimed is:

1. A display device, comprising:
a scan line;
a driving voltage line for transmitting a driving voltage;
a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region;
a second transistor including a second gate electrode, a second channel region overlapping the second gate electrode in the plan view, a second drain region electrically connected to the first gate electrode, and a second source region opposing the second drain region with respect to the second channel region;
a third transistor including a third gate electrode of the scan line, a third channel region overlapping the third gate electrode in the plan view, a third drain region electrically connected to the first gate electrode and extending from the second drain region in the plan view, and a third source region opposing the third drain region with respect to the third channel region; and
a fourth transistor including a fourth gate electrode of the scan line, a fourth channel region overlapping the fourth gate electrode in the plan view, a fourth drain region extending from the third source region in the plan view, and a fourth source region opposing the fourth drain region with respect to the fourth channel region;
a shielding part overlapping a boundary between the second source region and the second channel region, and does not overlap a boundary between the second drain region and the second channel region in the plan view; and
a light emitting diode comprising a pixel electrode, a light emitting layer, and a common electrode,
wherein the pixel electrode overlaps the boundary between the second source region and the second channel region and the boundary between the second drain region and the second channel region in the plan view, and
the driving voltage line overlaps a boundary between the third source region and the third channel region and a boundary between the third drain region and the third channel region in the plan view, and does not overlap a boundary between the fourth source region and the fourth channel region.

2. The display device of claim 1 , further comprising: a first connector connected to the first gate electrode and disposed in a different conductive layer from the first gate electrode, wherein the second drain region and the third drain region are electrically connected to the first gate electrode via the first connector.

3. The display device of claim 1 , wherein the shielding part is disposed between the first pixel electrode and the second channel region in a sectional view.

4. A display device, comprising:
a first scan line;
a driving voltage line for transmitting a driving voltage;
a light emitting diode comprising a pixel electrode, a light emitting layer, and a common electrode,
a first transistor including a first gate electrode, a first channel region overlapping the first gate electrode in a plan view, and a first source region and a first drain region opposing each other with respect to the first channel region;
a second transistor including a second gate electrode, a second channel region overlapping the second gate electrode in the plan view, a second drain region electrically connected to the first gate electrode, and a second source region opposing the second drain region with respect to the second channel region;
a third transistor including a third gate electrode of the first scan line, a third channel region overlapping the third gate electrode in the plan view, a third drain region electrically connected to the first gate electrode, and a third source region opposing the third drain region with respect to the third channel region;
a fourth transistor including a fourth gate electrode of the first scan line, a fourth channel region overlapping the fourth gate electrode in the plan view, a fourth drain region extending from the third source region, and a fourth source region opposing the fourth drain region with respect to the fourth channel region; and
a shielding part overlapping a boundary between the second source region and the second channel region, and does not overlap a boundary between the second drain region and the second channel region in the plan view,
wherein the pixel electrode overlaps the boundary between the second source region and the second channel region and the boundary between the second drain region and the second channel region in the plan view,
wherein the driving voltage line overlaps a boundary between the third source region and the third channel region and a boundary between the third drain region and the third channel region in the plan view, and does not overlap a boundary between the fourth source region and the fourth channel region,
wherein the display device further comprises a first connector connected to the first gate electrode and disposed in a different conductive layer from the first gate electrode, wherein the second drain region and the third drain region are electrically connected to the first gate electrode via the first connector, and
wherein the shielding part is in a same conductive layer as the first connector.

5. The display device of claim 4 , wherein the shielding part is disposed in a same conductive layer as the driving voltage line.

6. The display device of claim 5 , wherein the shielding part transmits a constant voltage.

7. The display device of claim 5 , further comprising:
a second scan line separated from the first scan line; and
a data line crossing the first scan line and the second scan line and for transmitting a data signal,
wherein the second scan line includes the second gate electrode.

Assignees

• Samsung Display Co Ltd
• Samsung Co Ltd

Inventors

• Choi Jun Won
• Kim Dong Soo
• Bang Hyun-Chol
• Pyon Chang Soo
• Lee Ji-Eun

Classifications

• H01L27/3216

  Electricity · mapped topic

• H01L27/32

  Electricity · mapped topic

• H01L27/3272 Primary

  Electricity · mapped topic

• H01L27/3262

  Electricity · mapped topic

• H01L29/78633

  Electricity · mapped topic