Semiconductor device and layout method of the same

Patent metadata

Field	Value
Publication number	US-12324246-B2
Application number	US-202217722683-A
Country	US
Kind code	B2
Filing date	Apr 18, 2022
Priority date	Jul 20, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A semiconductor device according to an embodiment of the present inventive concept includes a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having one or more gate structures and one or more active regions, and in some standard cells providing the same circuit and in standard cell regions at different locations, input lines or/and output lines are at different locations.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having two or more gate structures and two or more active regions,
wherein the plurality of standard cells comprise first standard cells in a first standard cell region and a second standard cell region, defined in different positions in at least one of the first direction or the second direction, and the first standard cells provide a same circuit,
wherein the first standard cell in the first standard cell region comprises a first input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the first standard cell region to each other, and a first output line connecting output wirings that are connected to two or more active regions of the first standard cell in the first standard cell region to each other, and
the first standard cell in the second standard cell region comprises a second input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the second standard cell region to each other, and a second output line connecting output wirings that are connected to two or more active regions of the first standard cell in the second standard cell region to each other,
wherein a position of the first input line in the first standard cell region is different from a position of the second input line in the second standard cell region, or a position of the first output line in the first standard cell region is different from a position of the second output line in the second standard cell region.

2. The semiconductor device of claim 1 , wherein, in the first direction, the position of the first input line in the first standard cell region is different from the position of the second input line in the second standard cell region, and
in the second direction, the position of the first input line in the first standard cell region is the same as the position of the second input line in the second standard cell region.

3. The semiconductor device of claim 1 , wherein, in the first direction, the position of the first output line in the first standard cell region is different from the position of the second output line in the second standard cell region, and
in the second direction, the position of the first output line in the first standard cell region is the same as the position of the second output line in the second standard cell region.

4. The semiconductor device of claim 1 , wherein, in the first direction, the position of the first input line in the first standard cell region is the same as the position of the second input line in the second standard cell region, and
in the second direction, the position of the first input line in the first standard cell region is different from the position of the second input line in the second standard cell region.

5. The semiconductor device of claim 1 , wherein, in the first direction, the position of the first output line in the first standard cell region is the same as the position of the second output line in the second standard cell region, and
in the second direction, the position of the first output line in the first standard cell region is different from the position of the second output line in the second standard cell region.

6. The semiconductor device of claim 1 , wherein, in each of the plurality of standard cells, the active regions extend in the first direction, and the gate structures extend in the second direction, and
each of the plurality of standard cells comprises active contacts connected between the active regions and the output wirings, gate vias connected between the gate structures and the input wirings, and active vias connected between the active contacts and the output wirings.

7. The semiconductor device of claim 6 , wherein the gate vias connected to the input wirings connected to each other by at least one of the first input line or the second input line are in different positions in the first direction.

8. The semiconductor device of claim 6 , wherein the output wirings connected to each other by at least one of the first output line or the second output line are connected to the active regions doped with impurities of different conductivity types by the active contacts.

9. The semiconductor device of claim 6 , wherein at least one of the two or more gate structures connected to each other by at least one of the first input line or the second input line is commonly connected to the input wirings by the gate vias.

10. The semiconductor device of claim 6 , wherein at least one of the two or more active regions connected to each other by at least one of the first output line or the second output line is commonly connected to the output wirings by the active contacts.

11. The semiconductor device of claim 1 , wherein at least one of the first input line or the second input line is at a same position as at least one of the gate structures in the first direction.

12. The semiconductor device of claim 1 , wherein, in the first direction, a width of each of the first input line, the second input line, the first output line, and the second output line is greater than a width of each of the gate structures.

13. The semiconductor device of claim 1 , further comprising: a plurality of power lines extending in the first direction and separated from each other in the second direction,
wherein the plurality of power lines are at a same height as the input wirings and the output wirings.

14. The semiconductor device of claim 13 , wherein at least one of the first input line, the second input line, the first output line, or the second output line extends in the second direction to intersect at least one of the plurality of power lines.

15. A semiconductor device comprising:
a plurality of standard cells in a first direction and a second direction, parallel to an upper surface of a substrate and intersecting with each other, and each of the plurality of standard cells having two or more gate structures and two or more active regions,
wherein the plurality of standard cells comprise first standard cells in a first standard cell region and a second standard cell region, defined in different positions in at least one of the first direction or the second direction, and the first standard cells provide a same circuit,
wherein the first standard cell in the first standard cell region comprises a first input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the first standard cell region to each other, and a first output line connecting output wirings that are connected to two or more active regions of the first standard cell in the first standard cell region to each other, and
the first standard cell in the second standard cell region comprises a second input line connecting input wirings that are connected to two or more gate structures of the first standard cell in the second standard cell region to each other, and a second output line connecting output wirings that are connected to two or more active regions of the first standard cell in the second standard cell region to each other,
wherein a position of the first input line in the first standard cell region is different from a position of the second input line in the second standard cell region, and a position of the first output line in the first standard cell region is different from a positi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaeha
• Kim Hyeongkyu
• Yoo Taejun
• Cheon Unseon

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title