Duplicate layering and routing

Patent metadata

Field	Value
Publication number	US-9893009-B2
Application number	US-201414151999-A
Country	US
Kind code	B2
Filing date	Jan 10, 2014
Priority date	Jan 10, 2014
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

In some embodiments, a semiconductor arrangement comprises a stacked interconnect structure comprising a first interconnect structure and a second interconnect structure. The stacked interconnect structure has a relatively larger aspect ratio than the first interconnect structure or the second interconnect structure, which reduces resistivity and improves performance. In some embodiments, a duplicate interconnect path is inserted into a design layout for a semiconductor arrangement. The duplicated interconnect path provides an additional path between a first net and a second net connected by an interconnect path. Connecting the first net and the second net by the interconnect path and the duplicated interconnect path reduces resistivity and improves performance. In some embodiments, a semiconductor arrangement comprises cell pin operatively coupled to a duplicate cell pin. The cell pin and the duplicate cell pin are operatively coupled to a logic structure to reduce resistivity and improve performance.

First claim

What is claimed is:

1. A semiconductor arrangement comprising a stacked interconnect structure, comprising:
a first interconnect structure formed within a first connectivity layer and having a first width;
a second interconnect structure formed over the first interconnect structure and within the first connectivity layer, wherein:
the second interconnect structure is in direct contact with the first interconnect structure, and
the second interconnect structure has a second width that is less than the first width;

a third interconnect structure formed over the second interconnect structure and formed within a second connectivity layer, wherein the third interconnect structure has the first width;
a first via extending between the second interconnect structure and the third interconnect structure, wherein:
the first via has a third width between the second interconnect structure and the third interconnect structure, and
the third width is less than the second width;

a fourth interconnect structure formed over the third interconnect structure; and
a second via between the third interconnect structure and the fourth interconnect structure, wherein the second via has a fourth width that is less than the second width and greater than the third width.

2. The semiconductor arrangement of claim 1 , wherein the first interconnect structure maintains the first width from a bottom surface of the first interconnect structure to a top surface of the first interconnect structure.

3. The semiconductor arrangement of claim 1 , wherein the first via is in direct contact with the second interconnect structure and the third interconnect structure.

4. The semiconductor arrangement of claim 1 , wherein the first interconnect structure and the second interconnect structure have a same height.

5. The semiconductor arrangement of claim 1 , wherein the second interconnect structure has a second interconnect aspect ratio smaller than a first interconnect aspect ratio of the first interconnect structure.

6. The semiconductor arrangement of claim 1 , wherein the fourth interconnect structure has a fourth interconnect aspect ratio different than a third interconnect aspect ratio of the third interconnect structure.

7. The semiconductor arrangement of claim 2 , wherein the second interconnect structure maintains the second width from a bottom surface of the second interconnect structure to a top surface of the second interconnect structure.

8. The semiconductor arrangement of claim 7 , wherein the third interconnect structure maintains the first width from a bottom surface of the third interconnect structure to a top surface of the third interconnect structure.

9. The semiconductor arrangement of claim 1 , wherein the second via is in direct contact with the third interconnect structure and the fourth interconnect structure.

10. The semiconductor arrangement of claim 9 , wherein the first via is in direct contact with the second interconnect structure and the third interconnect structure.

11. The semiconductor arrangement of claim 10 , wherein the fourth interconnect structure has the first width.

12. The semiconductor arrangement of claim 9 , wherein the fourth interconnect structure has the first width.

13. A semiconductor arrangement, comprising:
a first stacked interconnect structure, comprising:
a first interconnect structure formed within a first connectivity layer and having a first width; and
a second interconnect structure formed over the first interconnect structure and within the first connectivity layer, wherein:
the second interconnect structure is in direct contact with the first interconnect structure, and
the second interconnect structure has a second width different than the first width;

a second stacked interconnect structure formed over the first stacked interconnect structure and comprising:
a third interconnect structure formed within a second connectivity layer, wherein the third interconnect structure has the first width; and
a fourth interconnect structure formed over the third interconnect structure and within the second connectivity layer;

a first via in direct contact with the second interconnect structure and extending between the second interconnect structure and the third interconnect structure, wherein:
the first via has a third width between the second interconnect structure and the third interconnect structure, and
the third width is less than the second width;

a fifth interconnect structure formed within a third connectivity layer; and
a second via extending between the fourth interconnect structure and the fifth interconnect structure, wherein the second via has a fourth width that is less than the second width and greater than the third width.

14. The semiconductor arrangement of claim 13 , wherein the second width is less than the first width.

15. The semiconductor arrangement of claim 13 , wherein the fourth interconnect structure has the second width.

16. The semiconductor arrangement of claim 13 , wherein the fourth interconnect structure has the first width.

17. The semiconductor arrangement of claim 13 , wherein a height of the fifth interconnect structure is substantially equal to a combined height of the third interconnect structure and the fourth interconnect structure.

18. The semiconductor arrangement of claim 13 , wherein the first interconnect structure maintains the first width from a bottom surface of the first interconnect structure to a top surface of the first interconnect structure.

19. The semiconductor arrangement of claim 13 , wherein the first interconnect structure and the second interconnect structure have a same height.

20. A semiconductor arrangement, comprising:
a first stacked interconnect structure, comprising:
a first interconnect structure formed within a first connectivity layer and having a first width; and
a second interconnect structure formed over the first interconnect structure and within the first connectivity layer, wherein:
the second interconnect structure has a second width that is less than the first width,
the second interconnect structure is in direct contact with the first interconnect structure, and
the second interconnect structure maintains the second width from a bottom surface of the second interconnect structure to a top surface of the second interconnect structure;

a third interconnect structure over the second interconnect structure and having the first width;
a first via extending between the second interconnect structure and the third interconnect structure, wherein:
the first via is in direct contact with the second interconnect structure,
the first via has a third width between the second interconnect structure and the third interconnect structure, and
the third width is less than the second width;

a fourth interconnect structure formed over the third interconnect structure; and
a second via between the third interconnect structure and the fourth interconnect structure, wherein the second via has a fourth width that is less than the second width and greater than the third width.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Huang Yu
• Yu Chi Yeh
• Wang Chung Hsing

Classifications

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title