Semiconductor memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12324160-B2
Application number	US-202318396042-A
Country	US
Kind code	B2
Filing date	Dec 26, 2023
Priority date	Jan 30, 2020
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a peripheral transistor on a substrate;
forming a source layer over the peripheral transistor;
forming a stack structure over the source layer;
forming a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor;
forming conductive patterns in the stack structure;
forming a word line contact being electrically connected to at least one of the conductive patterns; and
forming a peripheral line to electrically connect the word line contact and the peripheral contact structure.

2. The method of claim 1 , wherein forming the peripheral contact structure includes:
forming a hole penetrating the stack structure and the source layer;
filling a portion of the hole by forming a peripheral insulating layer in the hole; and
completely filling the hole by forming a peripheral contact in the hole.

3. The method of claim 1 , further comprising forming a stepped structure by patterning the stack structure.

4. The method of claim 3 , wherein the peripheral contact structure is in contact with a step side surface which defines a surface of the stepped structure.

5. The method of claim 1 , wherein forming the peripheral contact structure further includes forming a dummy contact structure penetrating the stack structure and the source layer.

6. The method of claim 5 , wherein the dummy contact structure is electrically floated.

7. The method of claim 1 , wherein forming the conductive patterns in the stack structure includes:
forming a trench in the stack structure;
removing sacrificial patterns exposed through the trench; and
filling the conductive patterns in empty spaces in which the sacrificial patterns are removed.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek
• Jung Hye Yeong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title