Amplitude-to-phase error correction in a transceiver circuit

Patent metadata

Field	Value
Publication number	US-12323174-B2
Application number	US-202217890538-A
Country	US
Kind code	B2
Filing date	Aug 18, 2022
Priority date	Sep 16, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

Amplitude-to-phase (AM-PM) error correction in a transceiver circuit is provided. The transceiver circuit is configured to generate a radio frequency (RF) signal from a time-variant input vector for transmission in one or more transmission frequencies. In embodiments disclosed herein, the transceiver circuit is configured to determine a phase correction term from the time-variant input vector and apply the determined phase correction term to the time-variant input vector to thereby correct an AM-PM error(s) in the RF signal. By correcting the AM-PM error(s) in the transceiver circuit, it is possible to prevent undesired amplitude distortion and/or spectrum regrowth in any of the transmission frequencies, particularly when the RF signal is modulated across a wide modulation bandwidth (e.g., ≥200 MHz).

First claim

What is claimed is:

1. A transceiver circuit comprising:
a delay equalizer circuit configured to:
receive a time-variant input vector modulated for transmission in a plurality of transmission frequencies, the time-variant input vector is associated with a time-variant amplitude and a variable group delay that varies in accordance with the time-variant amplitude in each of the plurality of transmission frequencies;
equalize the time-variant input vector to thereby convert the variable group delay in each of the plurality of transmission frequencies into a respective constant group delay across the time-variant amplitude such that a respective variable phase error associated with the variable group delay in each of the plurality of transmission frequencies can become linearly related; and
generate a delay-equalized vector associated with the time-variant amplitude and having the respective constant group delay in a respective one of the plurality of transmission frequencies; and

a phase correction circuit configured to:
determine a reference phase offset corresponding to a reference frequency selected among the plurality of transmission frequencies;
superimpose the reference phase offset on the respective variable phase error of the respective one of the plurality of transmission frequencies to thereby determine a phase correction term configured to correct the respective variable phase error in the respective one of the plurality of transmission frequencies; and
apply the determined phase correction term to the delay-equalized vector to generate a delay-phase-equalized vector.

2. The transceiver circuit of claim 1 , further comprising:
a digital processing circuit configured to generate the time-variant input vector having the time-variant amplitude; and
a signal conversion circuit configured to generate a radio frequency (RF) signal based on the delay-phase-equalized vector.

3. The transceiver circuit of claim 1 , wherein the phase correction circuit comprises:
a first envelope detector configured to detect a first power envelope associated with the time-variant amplitude of the delay-equalized vector;
a phase correction lookup table (LUT) circuit configured to determine the reference phase offset corresponding to the reference frequency based on the detected first power envelope;
a phase equalizer circuit configured to equalize the delay-equalized vector to generate a phase-equalized vector having a second time-variant amplitude;
a second envelope detector configured to determine a second power envelope associated with the second time-variant amplitude;
a scaling circuit configured to:
determine a scaling factor as a function of the first power envelope and the second power envelope; and
scale the reference phase offset based on the determined scaling factor to thereby generate the phase correction term; and

a phase shifter circuit configured to apply the phase correction term to the delay-equalized vector to generate the delay-phase-equalized vector.

4. The transceiver circuit of claim 3 , wherein the scaling circuit comprises:
a divider configured to divide the second power envelope by the first power envelope to thereby determine the scaling factor; and
a multiplier configured to multiply the reference phase offset by the scaling factor to thereby generate the phase correction term.

5. The transceiver circuit of claim 3 , wherein the reference frequency is a center frequency among the plurality of transmission frequencies.

6. The transceiver circuit of claim 3 , wherein the filter circuit is further configured to equalize the delay-equalized vector based on finite impulse response (FIR) filter.

7. The transceiver circuit of claim 3 , wherein the phase correction circuit further comprises a delay tap configured to delay the delay-equalized vector to thereby align the first power envelope with the second power envelope at the scaling circuit.

8. The transceiver circuit of claim 1 , wherein the phase correction circuit comprises:
a first envelope detector configured to detect a first power envelope associated with the time-variant amplitude of the delay-equalized vector;
a delay lookup table (LUT) circuit configured to determine a reference delay offset corresponding to the reference frequency based on the determined first power envelope;
a filter circuit configured to equalize the delay-equalized vector to generate a first delay-equalized vector;
a delay tap configured to delay the delay-equalized vector to generate a second delay-equalized vector;
a scaling circuit configured to:
determine a scaling factor as a function of the first delay-equalized vector and the second delay-equalized vector; and
scale the reference delay offset based on the determined scaling factor to thereby generate a delay correction term;

a delay circuit configured to apply the delay correction term to the delay-equalized vector to generate a third delay-equalized vector associated with the time-variant amplitude;
a second envelope detector configured to detect a second power envelope associated with the time-variant amplitude of the third delay-equalized vector;
a phase correction LUT circuit configured to determine the phase correction term based on the determined second power envelope; and
a phase shifter circuit configured to apply the phase correction term to the third delay-equalized vector to generate the delay-phase-equalized vector.

9. The transceiver circuit of claim 8 , wherein the scaling circuit comprises:
a divider configured to divide the first delay-equalized vector by the second delay-equalized vector to thereby generate the scaling factor; and
a multiplier configured to multiply the reference delay offset by the scaling factor to generate the delay correction term.

10. The transceiver circuit of claim 8 , wherein the reference frequency is a center frequency among the plurality of transmission frequencies.

11. The transceiver circuit of claim 8 , wherein the filter circuit is further configured to equalize the delay-equalized vector based on finite impulse response (FIR) filter.

12. A transmission circuit comprising:
a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage for transmission in a plurality of transmission frequencies; and
a transceiver circuit comprising:
a digital processing circuit configured to generate a time-variant input vector modulated for transmission in the plurality of transmission frequencies, the time-variant input vector is associated with a time-variant amplitude and a variable group delay that varies in accordance with the time-variant amplitude in each of the plurality of transmission frequencies;

a delay equalizer circuit configured to:
receive the time-variant input vector;
equalize the time-variant input vector to thereby convert the variable group delay in each of the plurality of transmission frequencies into a respective constant group delay across the time-variant amplitude such that a respective variable phase error associated with the variable group delay in each of the plurality of transmission frequencies can become linearly related; and
generate a delay-equalized vector associated with the time-variant amplitude and having the respective constant group delay in a respective one of the plurality of transmission frequencies;

a phase correction circuit configured to:
determine a reference phase offset corresponding to a reference frequency selected among the plurality of transmission frequencies;
superimpose the reference phase offset on the respective variable phase error of the respective one of the plurality of transmission freq

Assignees

• Qorvo Us Inc

Inventors

• Khlat Nadim

Classifications

• H04B1/525

  with means for reducing leakage of transmitter signal into the receiver · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H03F3/19

  with semiconductor devices only · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03F1/3288 Primary

  to compensate phase shift as a function of the amplitude · CPC title