Circuit and method of shutdown for bias network in high voltage amplifier

Patent metadata

Field	Value
Publication number	US-12323113-B2
Application number	US-202117456781-A
Country	US
Kind code	B2
Filing date	Nov 29, 2021
Priority date	Nov 29, 2021
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A power amplifier has an amplifier cell with an input terminal receiving an input signal and an output terminal providing an output signal. A bias network is coupled to the output terminal of the amplifier cell to provide a bias signal to the amplifier cell. A shutdown circuit is coupled to the bias network to disable the bias network in response to the input signal. The shutdown circuit has a transistor with a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal. The shutdown circuit further has a first resistor with a first terminal coupled to the input terminal, and a second resistor with a first terminal coupled to a second terminal of the first resistor at a node, and a second terminal coupled to the power supply terminal. The control terminal of the transistor is coupled to the node.

First claim

What is claimed:

1. An amplifier, comprising:
an amplifier cell including an input terminal adapted for receiving an input signal and an output terminal adapted for providing an output signal;
a bias network coupled to the output terminal and providing a bias signal to the amplifier cell; and
a shutdown circuit coupled to the input terminal of the amplifier cell and further coupled to the bias network to disable the bias network in response to a non-assertion of the input signal and to enable the bias network in response to an assertion of the input signal.

2. The amplifier of claim 1 , wherein the shutdown circuit includes a transistor comprising a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal.

3. The amplifier of claim 2 , wherein the shutdown circuit further includes:
a first resistor comprising a first terminal coupled to the input terminal; and
a second resistor comprising a first terminal coupled to a second terminal of the first resistor at a first node, and a second terminal coupled to the power supply terminal, wherein the control terminal of the transistor is coupled to the first node.

4. The amplifier of claim 3 , wherein the shutdown circuit further includes a capacitor coupled between the first node and the power supply terminal.

5. The amplifier of claim 2 , wherein the bias network includes:
a first resistor comprising a first terminal coupled to the output terminal; and
a second resistor comprising a first terminal coupled to a second terminal of the first resistor, wherein a second terminal of the second resistor is coupled to the first conduction terminal of the transistor.

6. The amplifier of claim 1 , wherein the amplifier cell includes:
a first transistor comprising a first conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal; and
a second transistor comprising a first conduction terminal coupled to a second conduction terminal of the first transistor, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the power supply terminal.

7. A semiconductor device including an amplifier, comprising:
a first amplifier cell including an input terminal adapted for receiving a first input signal and an output terminal adapted for providing a first output signal;
a bias network coupled to the output terminal of the first amplifier cell; and
a shutdown circuit coupled to the input terminal of the amplifier cell and further coupled to the bias network to disable the bias network in response to a non-assertion of the first input signal.

8. The amplifier of claim 7 , wherein the shutdown circuit includes a transistor comprising a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal of the first amplifier cell.

9. The amplifier of claim 8 , wherein the shutdown circuit further includes:
a first resistor comprising a first terminal coupled to the input terminal of the first amplifier cell; and
a second resistor comprising a first terminal coupled to a second terminal of the first resistor at a first node, and a second terminal coupled to the power supply terminal, wherein the control terminal of the transistor is coupled to the first node.

10. The amplifier of claim 9 , wherein the shutdown circuit further includes a capacitor coupled between the first node and the power supply terminal.

11. The amplifier of claim 8 , wherein the bias network includes:
a first resistor comprising a first terminal coupled to the output terminal of the first amplifier cell; and
a second resistor comprising a first terminal coupled to a second terminal of the first resistor, wherein a second terminal of the second resistor is coupled to the first conduction terminal of the transistor.

12. The amplifier of claim 7 , wherein the first amplifier cell includes:
a first transistor comprising a first conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal of the first amplifier cell; and
a second transistor comprising a first conduction terminal coupled to a second conduction terminal of the first transistor, a second conduction terminal coupled to the output terminal of the first amplifier cell, and a control terminal coupled to the power supply terminal.

13. The amplifier of claim 7 , further including a second amplifier cell including an input terminal adapted for receiving a second input signal and an output terminal adapted for providing a second output signal, wherein the input terminal of the second amplifier cell is coupled to the input terminal of the first amplifier cell and the output terminal of the second amplifier cell is coupled to the output terminal of the first amplifier cell.

14. A method of making a semiconductor device including an amplifier, comprising:
providing a first amplifier cell including an input terminal adapted for receiving a first input signal and an output terminal adapted for providing a first output signal;
providing a bias network coupled to the output terminal of the first amplifier cell; and
providing a shutdown circuit coupled to the input terminal of the amplifier cell and further coupled to the bias network to disable the bias network in response to a non-assertion of the first input signal.

15. The method of claim 14 , wherein providing the shutdown circuit includes providing a transistor comprising a first conduction terminal coupled to the bias network, a second conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal of the first amplifier cell.

16. The method of claim 15 , wherein providing the shutdown circuit further includes:
providing a first resistor comprising a first terminal coupled to the input terminal; and
providing a second resistor comprising a first terminal coupled to a second terminal of the first resistor at a first node, and a second terminal coupled to the power supply terminal, wherein the control terminal of the transistor is coupled to the first node.

17. The method of claim 16 , wherein providing the shutdown circuit further includes providing a capacitor coupled between the first node and the power supply terminal.

18. The method of claim 15 , wherein providing the bias network includes:
providing a first resistor comprising a first terminal coupled to the output terminal of the first amplifier cell; and
providing a second resistor comprising a first terminal coupled to a second terminal of the first resistor, wherein a second terminal of the second resistor is coupled to the first conduction terminal of the first transistor.

19. The method of claim 14 , wherein providing the first amplifier cell includes:
providing a first transistor comprising a first conduction terminal coupled to a power supply terminal, and a control terminal coupled to the input terminal of the first amplifier cell; and
providing a second transistor comprising a first conduction terminal coupled to a second conduction terminal of the first transistor, a second conduction terminal coupled to the output terminal of the first amplifier cell, and a control terminal coupled to the power supply terminal.

20. The method of claim 14 , further including providing a second amplifier cell including an input terminal adapted for re

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Struble Wayne Mack

Classifications

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F1/223

  with MOSFET's · CPC title

• H03F1/0205

  in transistor amplifiers · CPC title

• H03F3/211

  using a combination of several amplifiers (H03F3/60 takes precedence) · CPC title