Efficient power electronics arrangement

Patent metadata

Field	Value
Publication number	US-12323071-B2
Application number	US-202418748045-A
Country	US
Kind code	B2
Filing date	Jun 19, 2024
Priority date	May 31, 2022
Publication date	Jun 3, 2025
Grant date	Jun 3, 2025

Abstract

A power electronics converter includes a substrate and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is comprised in a power semiconductor prepackage. An electrical connection side of the respective power semiconductor prepackage is spaced apart in a z direction from the substrate so as to define a prepackage gap between the substrate and the electrical connection side. At least a portion of the prepackage gap is filled with an electrically insulating material having voids. A converter parameter σ defined as an insulation fill factor divided by a maximum void size is greater than or equal to 10/mm. The insulation fill factor is defined as a cumulated volume of the voids subtracted from a volume of the electrically insulating material divided by the volume of the electrically insulating material.

First claim

The invention claimed is:

1. A power electronics converter comprising:
a commutation cell comprising a power circuit and a gate driver circuit, the power circuit comprising at least one power semiconductor switching element and at least one capacitor, each power semiconductor switching element of the at least one power semiconductor switching element having at least three terminals, the at least three terminals including a gate terminal, a source terminal, and a drain terminal,
wherein the gate driver circuit is electrically connected to and configured to provide switching signals to the gate terminal of each power semiconductor switching element of the at least one power semiconductor switching element, and
wherein a peak rated power output of the power electronics converter is greater than 25 KW, and a value of a converter parameter ε is greater than or equal to 10 26 V/s 4 , ε being equal to:

ε
=

f
max

×

❘
"\[LeftBracketingBar]"

d
⁢
v

d
⁢
t

❘
"\[RightBracketingBar]"

max

L
×
C

,

and
wherein:
f max is a maximum switching frequency of the switching signals;
|dv/dt| max is a maximum rate of change of a source-drain voltage of the at least one power semiconductor switching element during operation;
L is a parasitic inductance of the power circuit of the commutation cell; and
C is a total rated capacitance of the at least one capacitor of the power circuit.

2. The power electronics converter of claim 1 , wherein the value of the converter parameter ε is less than or equal to 10 29 V/s 4 .

3. The power electronics converter of claim 2 , wherein the value of the converter parameter ε is greater than or equal to 5×10 26 V/s 4 .

4. The power electronics converter of claim 1 , wherein the value of the converter parameter ε is in a range between 10 27 V/s 4 and 5×10 28 V/s 4 .

5. The power electronics converter of claim 1 , wherein the value of the converter parameter ε is in a range between 1.5×10 27 V/s 4 and 3×10 28 V/s 4 .

6. The power electronics converter of claim 1 , wherein a product of the parasitic inductance L of the power circuit of the commutation cell and the peak rated power output is in a range between 0.05 mHW and 1.5 mHW.

7. The power electronics converter of claim 1 , wherein a product of the maximum switching frequency f max and the maximum rate of change |dv/dt| max is greater than or equal to 0.3 PV/s 2 .

8. The power electronics converter of claim 1 , wherein a total rated capacitance of the power circuit of the commutation cell divided by the peak rated power output is less than 5 nF/W.

9. The power electronics converter of claim 1 , further comprising a multi-layer planar carrier substrate defining an x-y direction parallel to a planar surface of the multi-layer planar carrier substrate, and a z-direction perpendicular to the x-y direction, the multi-layer planar carrier substrate comprising a plurality of electrically conductive layers extending in the x-y direction and at least one electrical connection extending in the z-direction,
wherein each power semiconductor switching element of the at least one power semiconductor switching element is included in a power semiconductor prepackage,
wherein each power semiconductor prepackage further comprises an electrical connection from at least one terminal of the respective power semiconductor prepackage to an electrical connection side of the respective power semiconductor prepackage, the electrical connection extending in the z-direction through a solid insulating material, and
wherein at least one terminal of each power semiconductor switching element of the at least one power semiconductor switching element is connected to at least one electrically conductive layer of the plurality of electrically conductive layers of the multi-layer planar carrier substrate at the electrical connection side of the respective power semiconductor prepackage.

10. The power electronics converter of claim 9 , wherein for each power semiconductor prepackage, the electrical connection side of the respective semiconductor prepackage forms a flat surface, and the respective semiconductor prepackage is surface mounted at the electrical connection side to the planar surface of the multi-layer planar carrier substrate.

11. The power electronics converter of claim 10 , wherein for each power semiconductor prepackage, each electrical connection extending from at least one terminal of the at least three terminals of the respective power semiconductor switching element through the solid insulating material terminates at the flat surface of the respective semiconductor prepackage.

12. The power electronics converter of claim 11 , wherein each power semiconductor prepackage is surface mounted to the planar surface of the multi-layer planar carrier substrate by soldering, sintering, or gluing of the respective terminated electrical connection to an electrical connection of the multi-layer planar carrier substrate.

13. The power electronics converter of claim 12 , wherein the soldered, sintered, or glued connections space apart each power semiconductor prepackage from the planar surface of the multi-layer planar carrier substrate to define a gap, a size of the gap measured in the z-direction being less than or equal to 300 μm.

14. The power electronics converter of claim 9 , wherein the multi-layer planar carrier substrate is:
a rigid printed circuit board (PCB);
a flexible PCB; or
a ceramic carrier substrate.

15. The power electronics converter of claim 1 , wherein the power electronics converter is an AC-DC converter.

16. The power electronics converter of claim 1 , wherein the power electronics converter is a DC-DC converter.

17. An electrical propulsion unit (EPU) for an aircraft, the EPU comprising:
an electric motor; and
an AC-DC power electronics converter comprising:
a commutation cell comprising a power circuit and a gate driver circuit, the power circuit comprising at least one power semiconductor switching element and at least one capacitor, each power semiconductor switching element of the at least one power semiconductor switching element having at least three terminals, the at least three terminals including a gate terminal, a source terminal, and a drain terminal,

wherein the gate driver circuit is electrically connected to and configured to provide switching signals to the gate terminal of each power semiconductor switching element of the at least one power semiconductor switchi

Assignees

• Rolls Royce Deutschland Ltd & Co Kg

Inventors

• Waltrich Uwe
• Buchert Stanley
• Bohlländer Marco
• Müller Claus

Classifications

• H10W72/072 Primary

  of bump connectors · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W40/10

  Arrangements for heating · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title