Integrated circuit

Patent metadata

Field	Value
Publication number	US-12317751-B2
Application number	US-202318361373-A
Country	US
Kind code	B2
Filing date	Jul 28, 2023
Priority date	Sep 28, 2018
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a metallization pattern having a first conductive feature and a second conductive feature;
an etch stop layer over the metallization pattern, wherein the etch stop layer has a first portion over the first conductive feature and a second portion over the second conductive feature;
a memory device over the first portion of the etch stop layer;
a bottom electrode via at least partially in the first portion of the etch stop layer and electrically connecting the memory device to the first conductive feature;
a third conductive feature at least partially in the second portion of the etch stop layer and electrically connected to the second conductive feature; and
a dielectric feature between the first and second portions of the etch stop layer, wherein the dielectric feature is in contact with a sidewall of the first portion of the etch stop layer and a sidewall of the second portion of the etch stop layer.

2. The integrated circuit of claim 1 , wherein a bottom of the dielectric feature is lower than a bottom surface of the etch stop layer.

3. The integrated circuit of claim 1 , wherein the dielectric feature is spaced apart from the first conductive feature and the second conductive feature.

4. The integrated circuit of claim 1 , wherein the dielectric feature comprises oxide.

5. The integrated circuit of claim 1 , further comprising:
a metal-containing dielectric layer over and in contact with the first portion of the etch stop layer, wherein the second portion of the etch stop layer is free from coverage by the metal-containing dielectric layer.

6. The integrated circuit of claim 5 , wherein the dielectric feature is free from coverage by the metal-containing dielectric layer.

7. The integrated circuit of claim 1 , further comprising:
an interlayer dielectric layer surrounding the third conductive feature and in contact with the dielectric feature.

8. The integrated circuit of claim 7 , wherein the interlayer dielectric layer is further in contact with the second portion of the etch stop layer.

9. An integrated circuit, comprising:
a metallization layer having a first conductive feature, a second conductive feature, and an inter-metal dielectric layer surrounding the first and second conductive features;
an etch stop layer over the metallization layer, wherein the etch stop layer has a first portion over the first conductive feature and a second portion over the second conductive feature, wherein the first portion of the etch stop layer is spaced apart from the second portion of the etch stop layer in a cross-sectional view, and a sidewall of the first portion of the etch stop layer facing the second portion of the etch stop layer vertically overlaps the inter-metal dielectric layer;
a dielectric feature between the first and second portions of the etch stop layer, wherein the dielectric feature is in contact with the sidewall of the first portion of the etch stop layer and a sidewall of the second portion of the etch stop layer;
a memory device over the first portion of the etch stop layer;
a bottom electrode via at least partially in the first portion of the etch stop layer and electrically connecting the memory device to the first conductive feature; and
a third conductive feature at least partially in the second portion of the etch stop layer and electrically connected to the second conductive feature.

10. The integrated circuit of claim 9 , further comprising:
an interlayer dielectric layer surrounding the third conductive feature and in contact with the first and second portions of the etch stop layer in the cross-sectional view.

11. The integrated circuit of claim 9 , further comprising:
a metal-containing dielectric layer over the first portion of the etch stop layer, wherein the bottom electrode via is further in the metal-containing dielectric layer.

12. The integrated circuit of claim 11 , wherein the second portion of the etch stop layer is free from coverage by the metal-containing dielectric layer.

13. The integrated circuit of claim 11 , wherein the metal-containing dielectric layer is an aluminum-based layer.

14. An integrated circuit, comprising:
a first metallization layer having a first conductive feature, a second conductive feature, and a first dielectric layer surrounding the first and second conductive features;
an etch stop layer over the first metallization layer, wherein the etch stop layer has a first portion over the first conductive feature and a second portion over the second conductive feature;
a memory device over the first portion of the etch stop layer;
a bottom electrode via at least partially in the first portion of the etch stop layer and electrically connecting the memory device to the first conductive feature;
a third conductive feature at least partially in the second portion of the etch stop layer and electrically connected to the second conductive feature;
an interlayer dielectric layer surrounding the third conductive feature; and
a dielectric feature between the first and second portions of the etch stop layer, wherein the dielectric feature is in contact with the interlayer dielectric layer and the first dielectric layer of the first metallization layer.

15. The integrated circuit of claim 14 , wherein a bottom of the dielectric feature is higher than a bottom surface of the first conductive feature and lower than a top surface of the first conductive feature.

16. The integrated circuit of claim 14 , wherein the dielectric feature comprises the same material as that of the interlayer dielectric layer.

17. The integrated circuit of claim 14 , wherein the dielectric feature comprises a different material than that of the interlayer dielectric layer.

18. The integrated circuit of claim 14 , further comprising:
a metal-containing dielectric layer over and in contact with the first portion of the etch stop layer, wherein the interlayer dielectric layer is in contact with the second portion of the etch stop layer.

19. The integrated circuit of claim 18 , wherein the interlayer dielectric layer is in contact with a sidewall of the metal-containing dielectric layer.

20. The integrated circuit of claim 14 , further comprising:
a second metallization layer having a fourth conductive feature, a fifth conductive feature, and a second dielectric layer surrounding the fourth and fifth conductive features, wherein the fourth conductive feature is electrically connected to the memory device, and the fifth conductive feature is electrically connected to the third conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Tai-Yen
• Huang Chien-Chung
• Chen Yu-Shu
• Yang Sin-Yi
• Wang Chen-Jung
• Lin Han-Ting
• Ting Chih-Yuan
• Shieh Jyu-Horng
• Wei Hui-Hsien

Classifications

• H10N50/80

  Constructional details · CPC title

• H10B61/00 Primary

  Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10B61/10

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title