Isolation device with safety fuse

Patent metadata

Field	Value
Publication number	US-12317518-B2
Application number	US-202117512415-A
Country	US
Kind code	B2
Filing date	Oct 27, 2021
Priority date	Oct 27, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.

First claim

What is claimed is:

1. A semiconductor device comprising:
first and second conductive layers positioned over a substrate;
at least one dielectric layer between the first and second conductive layers, wherein the at least one dielectric layer is positioned over at least a portion of the second conductive layer, and the first conductive layer is positioned over a portion of the at least one dielectric layer; and
a third conductive layer positioned over the substrate and conductively connected to the second conductive layer and the substrate, wherein the third conductive layer includes a fusible link having fuse body connected to two fuse terminals by corresponding tapered metal portions.

2. The semiconductor device of claim 1 , further comprising an interconnection network conductively connected to the third conductive layer and to the second conductive layer.

3. The semiconductor device of claim 1 , wherein the portion of the at least one dielectric layer is a first portion, and the third conductive layer is positioned over a second portion of the at least one dielectric layer.

4. The semiconductor device of claim 1 , wherein the fusible link is located at a same metal layer as the first conductive layer.

5. The semiconductor device of claim 1 , wherein the substrate is located in a device package, a first wire is connected between a first package terminal and the first conductive layer, and a second wire is connected between a second package terminal and the fusible link.

6. The semiconductor device of claim 5 , wherein the device package is a molded plastic package.

7. An integrated circuit (IC) comprising:
upper and lower electrodes located over a substrate, and separated by a dielectric layer, the lower electrode located directly between the upper electrode and the substrate;
an interconnect network that conductively connects the lower electrode to the substrate and to a first terminal of a fusible link; and
a wire bonded to a second terminal of the fusible link.

8. The IC as recited in claim 7 , wherein the fusible link is at a same metal level as the upper electrode.

9. The IC as recited in claim 7 , wherein the interconnect network includes a plurality of vertically stacked metal portions.

10. The IC as recited in claim 7 , wherein the fusible link is connected to the first terminal and second terminal by tapered portions with a maximum width less than a width of the first and second terminals.

11. The IC as recited in claim 7 , wherein the lower electrode is connected to a transistor gate electrode.

12. The IC as recited in claim 7 , wherein the upper and lower electrodes include first and second plates of a parallel plate capacitor.

13. A semiconductor device comprising:
first and second conductive layers positioned over a substrate located in a device package;
at least one dielectric layer between the first and second conductive layers, wherein the at least one dielectric layer is positioned over at least a portion of the second conductive layer, and the first conductive layer is positioned over a portion of the at least one dielectric layer;
a third conductive layer positioned over the substrate and conductively connected to the second conductive layer and the substrate, wherein the third conductive layer includes a fusible link;
a first wire connected between a first package terminal and the first conductive layer; and
a second wire is connected between a second package terminal and the fusible link.

14. The semiconductor device of claim 13 , further comprising an interconnection network conductively connected to the third conductive layer to the second conductive layer.

15. The semiconductor device of claim 13 , wherein the portion of the at least one dielectric layer is a first portion, and the third conductive layer is positioned over a second portion of the at least one dielectric layer.

16. The semiconductor device of claim 13 , wherein the fusible link is located at a same metal layer as the first conductive layer.

17. The semiconductor device of claim 13 , wherein the device package is a molded plastic package.

Assignees

• Texas Instruments Inc

Inventors

• Guo Honglin
• Bonifield Thomas Dyer

Classifications

• H10W20/493 Primary

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H01H85/0241

  Structural association of a fuse and another component or apparatus (switches with built-in fuses H01H9/10, spark-gap arresters H01H85/44, transformers and inductances H01F27/402, capacitors H01G2/14, lamps H01K1/66, semiconductors H10W20/493 or H10W42/80) · CPC title

• H01H2085/0283

  Structural association with a semiconductor device · CPC title

• H01H2229/05

  Forming; Half-punching · CPC title

• H01H2239/006

  Containing a capacitive switch or usable as such · CPC title