Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-12315726-B2
Application number	US-202418595554-A
Country	US
Kind code	B2
Filing date	Mar 5, 2024
Priority date	Oct 31, 2018
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.

First claim

What is claimed is:

1. A method for manufacturing an integrated circuit, the method comprising:
forming a first patterned mask over a target layer, the first patterned mask having a first pattern and a second pattern;
forming a multi-layer gap-filling material into an opening between the first pattern and the second pattern of the first patterned mask, the multi-layer gap-filling material extending above top surfaces of the first patterned mask;
removing portions of the multi-layer gap-filling material above the top surfaces of the first patterned mask; and
patterning the target layer to form a patterned target layer, patterning the target layer using remaining portions of the multi-layer gap-filling material as a mask.

2. The method of claim 1 , wherein the patterned target layer is conductive, further comprising:
filling the patterned target layer with a dielectric material.

3. The method of claim 1 , wherein the patterned target layer is an insulating material, further comprising:
filling the patterned target layer with a conductive material.

4. The method of claim 1 , wherein the remaining portions of the multi-layer gap-filling material have a V-shaped cross-section.

5. The method of claim 1 , wherein forming the multi-layer gap-filling material comprises forming a first layer, wherein the first layer extends along sidewalls of the opening, wherein at least a portion of a bottom of the opening remains free of the first layer.

6. The method of claim 1 , further comprising, prior to forming the multi-layer gap-filling material, forming a mask layer over a top surface and along sidewalls of the first patterned mask, wherein the multi-layer gap-filling material is formed over the mask layer.

7. The method of claim 6 , further comprising removing the mask layer from an upper surface of the first patterned mask.

8. The method of claim 6 , further comprising, prior to patterning the target layer, removing the first patterned mask.

9. The method of claim 6 , further wherein patterning the target layer uses remaining portions of the mask layer as part of the mask.

10. A method for manufacturing an integrated circuit, the method comprising:
forming a first patterned layer over a target layer, the first patterned layer having a first pattern feature and a second pattern feature;
forming a first mask layer over the first patterned layer;
patterning the first mask layer to form a gap, wherein the gap extends between the first pattern feature and the second pattern feature;
forming a multi-layer gap-filling material into the gap, the multi-layer gap-filling material extending above top surfaces of the first patterned layer;
removing the first mask layer and portions of the multi-layer gap-filling material above an upper surface of the first patterned layer;
removing the first patterned layer; and
patterning the target layer using remaining portions of the multi-layer gap-filling material as a mask.

11. The method of claim 10 , further comprising, prior to forming the first mask layer, forming a second mask layer over the first patterned layer, wherein the first mask layer is formed over the second mask layer, wherein a portion of the second mask layer is exposed in the gap.

12. The method of claim 11 , further comprising, after removing the first patterned layer, removing portions of the second mask layer from over an upper surface of the first patterned layer.

13. The method of claim 12 , wherein patterning the target layer further comprises using remaining portions of the second mask layer as part of the mask.

14. The method of claim 13 , wherein forming the multi-layer gap-filling material comprises forming a first gap-filling layer and a second gap-filling layer over the first gap-filling layer, further comprising:
prior to patterning the target layer, removing a first layer of the multi-layer gap-filling material.

15. The method of claim 10 , wherein forming the multi-layer gap-filling material comprises forming a first gap-filling layer and a second gap-filling layer over the first gap-filling layer, further comprising:
prior to patterning the target layer, thinning a width of the first gap-filling layer.

16. A method for manufacturing an integrated circuit, the method comprising: forming a first patterned mask over a target layer, the first patterned mask having a first feature pattern and a second feature pattern;
forming a second patterned mask over the first patterned mask, the second patterned mask having an opening, the opening being between the first feature pattern and the second feature pattern of the first patterned mask;
forming a mask feature in the opening, forming the mask feature comprising:
depositing a first gap-filling material along sidewalls of the opening; and
depositing a second gap-filling material over the first gap-filling material within the opening, the second gap-filling material being different from the first gap-filling material;

removing the second patterned mask;
thinning the mask feature to form a thinned mask feature; and
patterning the target layer using the thinned mask feature as a first mask.

17. The method of claim 16 , wherein thinning the mask feature comprises removing the first gap-filling material prior to removing the second patterned mask.

18. The method of claim 16 , wherein thinning the mask feature is performed at least in part by etching the first gap-filling material after removing the second patterned mask.

19. The method of claim 16 , further comprising:
prior to forming the second patterned mask, forming a mask layer along sidewalls of the first patterned mask; and
after removing the second patterned mask, patterning the mask layer using the thinned mask feature as a second mask.

20. The method of claim 19 , further comprising, after removing the second patterned mask, removing the first patterned mask, wherein patterning the target layer uses at least a portion of the mask layer as part of the first mask.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Ching-Yu
• Shiu Jung-Hau
• Wang Jen Hung
• Lee Tze-Liang

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6905

  being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H · CPC title