Memory device and program operation thereof

Patent metadata

Field	Value
Publication number	US-12315568-B2
Application number	US-202418404690-A
Country	US
Kind code	B2
Filing date	Jan 4, 2024
Priority date	Aug 27, 2021
Publication date	May 27, 2025
Grant date	May 27, 2025

Abstract

In certain aspects, a memory device includes memory cells, word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is coupled to the word lines and configured to apply program pulses to a selected word line of the word lines in a program operation, obtain a number of occurrences of suspensions during the program operation, and determine a limit on a number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation.

First claim

What is claimed is:

1. A memory device, comprising:
memory cells;
word lines coupled to the memory cells; and
a peripheral circuit coupled to the word lines and configured to:
apply program pulses to a selected word line of the word lines in a program operation;
obtain a number of occurrences of suspensions during the program operation; and
determine an upper limit on a total number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation, wherein the upper limit represents a maximum number of program pulses allowed in the program operation, and the total number of program pulses for the program operation is smaller than or equal to the upper limit.

2. The memory device of claim 1 , wherein the peripheral circuit is further configured to:
in response to the number of occurrences of the suspensions being equal to zero, determine the upper limit to be a first number.

3. The memory device of claim 2 , wherein the peripheral circuit is further configured to:
in response to the number of occurrences of the suspensions being greater than zero, determine the upper limit to be a second number, wherein the second number is greater than the first number.

4. The memory device of claim 1 , wherein the peripheral circuit is further configured to:
in response to the total number of program pluses in the program operation reaching the upper limit, terminate the program operation.

5. The memory device of claim 1 , wherein to determine the upper limit on the total number of program pulses, the peripheral circuit comprises control logic configured to calculate the upper limit based on a weight and the number of occurrences of the suspensions.

6. The memory device of claim 5 , wherein to calculate the upper limit, the control logic is configured to:
calculate a weighted number of suspensions based on the weight and the number of occurrences of the suspensions; and
determine the upper limit on the total number of program pulses based on the weighted number of occurrences of the suspensions.

7. The memory device of claim 5 , wherein
the peripheral circuit comprises a word line driver coupled to the word lines;
the word line driver is configured to apply the program pulses with incremental voltages to the select word line; and
a resumed incremental voltage of a program pulse immediately after a resumption of the program operation is smaller than a default incremental voltage of the program pulses.

8. The memory device of claim 7 , wherein the weight is based on a difference between the resumed incremental voltage and the default incremental voltage.

9. The memory device of claim 5 , wherein the weight is set based on a location of the select word line among the word lines.

10. The memory device of claim 1 , wherein to obtain the number of occurrences of the suspensions, the peripheral circuit comprises:
a control logic configured to obtain the number of occurrences of the suspensions during the program operation; and
a register coupled to the control logic and configured to store the number of occurrences of the suspensions.

11. The memory device of claim 1 , wherein to obtain the number of occurrences of the suspensions, the peripheral circuit comprises control logic configured to receive the number of occurrences of the suspensions during the program operation from a memory controller.

12. A system, comprising:
a memory device comprising:
memory cells;
word lines coupled to the memory cells; and
a peripheral circuit coupled to the word lines and configured to:
receive a program command and apply program pulses to a selected word line of the word lines in a program operation;
obtain a number of occurrences of suspensions during the program operation; and
determine an upper limit on a total number of program pulses for the program operation based on a number of occurrences of the suspensions during the program operation, wherein the upper limit represents a maximum number of program pulses allowed in the program operation, and the total number of program pulses for the program operation is smaller than or equal to the upper limit; and

a memory controller coupled to the memory device and configured to transmit the program command to the peripheral circuit.

13. The system of claim 12 , wherein the memory controller is further configured to transmit suspend commands after the program command to the peripheral circuit to cause the suspensions during the program operation.

14. The system of claim 13 , wherein the memory controller is further configured to:
record the number of occurrences of suspensions based on a number of the suspend commands transmitted to the peripheral circuit; and
transmit the number of occurrences of suspensions to the peripheral circuit.

15. The system of claim 13 , wherein the peripheral circuit is further configured to record the number of occurrences of suspensions based on a number of the suspend commands received from the memory controller.

16. A method for operating a memory device, the memory device comprising memory cells and word lines coupled to the memory cells, the method comprising:
applying program pulses to a selected word line of the word lines in a program operation;
obtaining a number of occurrences of suspensions during the program operation; and
determining an upper limit on a total number of program pulses for the program operation based on the number of occurrences of the suspensions during the program operation, wherein the upper limit represents a maximum number of program pulses allowed in the program operation, and the total number of program pulses for the program operation is smaller than or equal to the upper limit.

17. The method of claim 16 , further comprising, in response to the total number of program pluses in the program operation reaching the upper limit, terminating the program operation.

18. The method of claim 16 , wherein determining the upper limit comprises calculating the upper limit based on a weight and the number of occurrences of the suspensions.

19. The method of claim 18 , wherein calculating the upper limit comprises:
calculating a weighted number of occurrences of the suspensions based on the weight and the number of occurrences of the suspensions; and
determining the upper limit on the total number of program pulses based on the weighted number of occurrences of the suspensions.

20. The method of claim 16 , wherein obtaining the number of occurrences of the suspensions comprises:
obtaining the number of occurrences of the suspensions during the program operation; and
storing the number of occurrences of the suspensions.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Huangpeng
• Du Zhichao
• Jiang Ke
• Luo Cong
• Song Daesik

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title