Memory device and program operation thereof

Patent metadata

Field	Value
Publication number	US-11908522-B2
Application number	US-202117488701-A
Country	US
Kind code	B2
Filing date	Sep 29, 2021
Priority date	Aug 27, 2021
Publication date	Feb 20, 2024
Grant date	Feb 20, 2024

Abstract

In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.

First claim

What is claimed is:

1. A memory device, comprising:
memory cells; and
a peripheral circuit coupled to the memory cells and configured to:
initiate a program operation on a selected memory cell of the memory cells;
obtain a number of occurrences of one or more suspensions during the program operation; and
determine a limit on a number of program pulses for the program operation based on the number of occurrences of the one or more suspensions during the program operation.

2. The memory device of claim 1 , wherein the peripheral circuit is further configured to, in response to the number of program pluses in the program operation reaching the limit, terminate the program operation.

3. The memory device of claim 1 , wherein to determine the limit on the number of program pulses, the peripheral circuit comprises control logic configured to calculate the limit based on a default program pulse limit, a weight, and the number of occurrences of the one or more suspensions.

4. The memory device of claim 3 , wherein to calculate the limit, the control logic is configured to:
calculate a weighted number of suspensions based on the weight and the number of occurrences of the one or more suspensions; and
adjust the default program pulse limit based on the weighted number of occurrences of the suspensions.

5. The memory device of claim 3 , further comprising word lines coupling the peripheral circuit to the memory cells, wherein
the peripheral circuit comprises a word line driver coupled to a select word line of the word lines that is coupled to the select memory cell;
the word line driver is configured to apply the program pulses with incremental voltages to the select word line; and
a resumed incremental voltage of a program pulse immediately after a resumption of the program operation is smaller than a default incremental voltage of the program pulses.

6. The memory device of claim 5 , wherein the weight is set based on a difference between the resumed incremental voltage and the default incremental voltage.

7. The memory device of claim 5 , wherein the weight is set based on a location of the select word line among the word lines.

8. The memory device of claim 3 , wherein the weight is set based on the default program pulse limit.

9. The memory device of claim 1 , wherein to obtain the number of occurrences of the one or more suspensions, the peripheral circuit comprises:
control logic configured to track the number of occurrences of the one or more suspensions during the program operation; and
a register coupled to the control logic and configured to store the tracked number of occurrences of the one or more suspensions.

10. The memory device of claim 1 , wherein to obtain the number of occurrences of the one or more suspensions, the peripheral circuit comprises control logic configured to receive the number of occurrences of the one or more suspensions during the program operation from a memory controller.

11. A system, comprising:
a memory device configured to store data and comprising:
memory cells; and
a peripheral circuit coupled to the memory cells and configured to:
initiate a program operation on a selected memory cell of the memory cells;
obtain a number of occurrences of one or more suspensions during the program operation; and
determine a limit on a number of program pulses for the program operation based on the number of occurrences of the one or more suspensions during the program operation; and

a memory controller coupled to the memory device and configured:
transmit a program command to the peripheral circuit to initiate the program operation; and
transmit one or more suspend commands after the program command to the peripheral circuit to cause the one or more suspensions during the program operation.

12. A method for operating a memory device comprising memory cells, the method comprising:
initiating a program operation on a selected memory cell of the memory cells;
obtaining a number of occurrences of one or more suspensions during the program operation; and
determining a limit on a number of program pulses for the program operation based on the number of occurrences of the one or more suspensions during the program operation.

13. The method of claim 12 , further comprising, in response to the number of program pluses in the program operation reaching the limit, terminating the program operation.

14. The method of claim 12 , wherein determining the limit comprises calculating the limit based on a default program pulse limit, a weight, and the number of occurrences of the one or more suspensions.

15. The method of claim 14 , wherein calculating the limit comprises:
calculating a weighted number of occurrences of the one or more suspensions based on the weight and the number of occurrences of the one or more suspensions; and
adjusting the default program pulse limit based on the weighted number of occurrences of the one or more suspensions.

16. The method of claim 14 , wherein
the memory device further comprises a select word line coupled to the select memory cell; and
the method further comprises applying the program pulses with incremental voltages to the select word line, a resumed incremental voltage of a program pulse immediately after a resumption of the program operation being smaller than a default incremental voltage of the program pulses.

17. The method of claim 16 , wherein the weight is set based on a difference between the resumed incremental voltage and the default incremental voltage.

18. The method of claim 16 , wherein the weight is set based on a location of the select word line among word lines or the default program pulse limit.

19. The method of claim 12 , wherein obtaining the number of occurrences of the one or more suspensions comprises:
tracking the number of occurrences of the one or more suspensions during the program operation; and
storing the tracked number of occurrences of the one or more suspensions.

20. The method of claim 12 , wherein obtaining the number of occurrences of the one or more suspensions comprises receiving the number of occurrences of the one or more suspensions during the program operation.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhang Huangpeng
• Du Zhichao
• Jiang Ke
• Luo Cong
• Song Daesik

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title