Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12310112-B2
Application number	US-202218016422-A
Country	US
Kind code	B2
Filing date	Jan 28, 2022
Priority date	Jan 28, 2022
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

The embodiment of the present disclosure provides a display substrate including a plurality of gate lines and a plurality of data lines. The plurality of gate lines each extend along a first direction, and the plurality of data lines each extend along a second direction. The plurality of data lines are spatially crossed with the plurality of gate lines to define a plurality of pixel regions, and at least one sub-pixel is provided in each of the plurality of pixel regions. At least three sub-pixels adjacent to each other along the second direction form one of a plurality of pixels. All the sub-pixels within one of the plurality of pixels are coupled to a same data line of the plurality of data lines.

First claim

What is claimed is:

1. A display substrate comprises a base substrate, a plurality of gate lines and a plurality of data lines, wherein
the plurality of gate lines each extend along a first direction, and the plurality of data lines each extend along a second direction,
the plurality of data lines are spatially crossed with the plurality of gate lines to define a plurality of pixel regions, and at least one sub-pixel is provided in each of the plurality of pixel regions,
at least three sub-pixels adjacent to each other along the second direction form one of a plurality of pixels;
all the sub-pixels within one of the plurality of pixels are coupled to a same data line of the plurality of data lines,
each of the pixels comprises a first electrode and a second electrode on the base substrate, the first electrode and the second electrode are disposed away from the base substrate in sequence, the first electrode comprises a plurality of first sub-electrodes and the second electrode comprises a plurality of second sub-electrodes, an orthographic projections of the first sub-electrode on the base substrate at least partially overlaps an orthographic projections of the second sub-electrode on the base substrate, and the second sub-electrodes adjacent to each other along the first direction and/or the second direction are coupled to each other to form a second block electrode serving as a touch electrode,
each second sub-electrode is provided with a plurality of gaps arranged along the second direction, spaced apart from each other, and each extending along the first direction,
the sub-pixels are arranged in an array, one data line is disposed between any two adjacent columns of the sub-pixels, each of the sub-pixels is divided to two domain regions by a domain boundary extending along the first direction, and the domain boundaries of a column of sub-pixels are on a same straight line, and an orthographic projection of each of the touch signal lines on the base substrate overlaps orthographic projections of the domain boundaries of the column of sub-pixels on the base substrate,
each of the sub-pixels comprises one transistor, the second block electrode is on a side of the touch signal line away from the base substrate, a first insulation layer is between the second block electrode and the touch signal line, the second block electrode is coupled to the touch signal line via a first through hole formed in the first insulation layer, and an orthographic projection of the first through hole on the base substrate is on a side, away from the transistor, of the opening region of the sub-pixel where the first through hole is located,
in the pixel region where the first through hole is formed, the plurality of gaps in the second sub-electrode comprise a third gap set and a fourth gap set arranged along the second direction, the third gap set comprises at least one gap and the fourth gap set comprises at least one gap, the third gap set and the first through hole are arranged along the first direction, and the fourth gap set and the transistor are arranged along the first direction, the touch signal line on the domain boundaries divides each of the at least one gap of the third gap set into two sub-gaps and divides the each of at least one gap of the fourth gap set into two sub-gaps, a length of the sub-gap of the third gap set on a side of the touch signal line away from the first through hole is greater than a length of the sub-gap of the third gap set on a side of the touch signal line proximal to the first through hole, and a length of the sub-gap of the fourth gap set on a side of the touch signal line proximal to the transistor is less than a length of the sub-gap of the fourth gap set on a side of the touch signal line away from the transistor.

2. The display substrate of claim 1 , wherein
one sub-pixel is disposed in each of the plurality of pixel regions,
all the sub-pixels of each of the pixels are arranged along the second direction in sequence, and
all the sub-pixels of each of the pixels are coupled to different gate lines of the plurality of gate lines, respectively.

3. The display substrate of claim 1 , wherein the formed second block electrode comprises a plurality of second block electrodes arranged in an array;
each of the plurality of second sub-electrodes comprises the same number of second sub-electrodes arranged in an array,
and
in two adjacent rows of the second sub-electrodes in two second block electrodes adjacent to each other along the second direction, one row of the second sub-electrodes is disconnected from the other row of the second sub-electrodes.

4. The display substrate of claim 3 , wherein
the transistor is located at a position where the data line crosses the gate line; and an orthographic projection of the transistor on the base substrate is between an orthographic projection, on the base substrate, of an opening region of the sub-pixel where the transistor is located and an orthographic projection, on the base substrate, of the data line coupled to the sub-pixel,
a gate electrode of the transistor is proximal to the gate line coupled to the transistor, a source electrode of the transistor is proximal to the data line coupled to the transistor, and a drain electrode of the transistor is proximal to a gate electrode of another transistor adjacent to the transistor along the second direction,
the drain electrode is coupled to the first sub-electrode,
two second sub-electrodes adjacent to each other along the first direction in the second block electrode are coupled to each other via a first connection portion, and
the first connection portion extends along the first direction, and an orthographic projection of the first connection portion on the base substrate and an orthographic projection of the data line on the base substrate intersect each other.

5. The display substrate of claim 4 , wherein the first connection portion is in the same layer as the second sub-electrode.

6. The display substrate of claim 5 , further comprising a second connection portion configured to couple two second sub-electrodes adjacent to each other along the second direction in the second block electrode.

7. The display substrate of claim 4 , further comprising a plurality of touch signal line sets, each of the plurality of touch signal line sets comprising a plurality of touch signal lines,
each of the plurality of touch signal lines extends along the second direction,
each of the plurality touch signal line sets corresponds to one column of second block electrodes, and
each of the second block electrodes is coupled to at least one of the plurality of touch signal lines.

8. The display substrate of claim 1 , wherein the touch signal line is located at the same layer as the data line, and the source electrode and drain electrode of the transistor.

9. The display substrate of claim 8 , wherein one of the touch signal lines is coupled to a corresponding one of the second block electrodes through a plurality of the first through holes arranged along the second direction;
multiple gate lines are disposed between any two adjacent first through holes of the plurality of the first through holes,
in a row of the pixel regions, in which the first through hole is formed, with the pixel regions arranged along the first direction, the first through hole and the drain electrode of the transistor are respectively located on different straight lines extending along the first direction, and a minimum distance between the first through hole and one of the gate lines closest to the first through hole is less than a minimum distance between a position where the drain electrode of the transistor is coupled to the first sub-electrode and the g

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ma Xiaoye
• Zhang Ran
• Xie Yongxian
• Zhang Mingfei
• Yin Xiaofeng
• Yang Tong
• Lv Fengzhen
• Wang Yongcan
• Gu Xiaofang

Classifications

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title