In-Cell Touch Panel and Display Device

US2016378254A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016378254-A1
Application numberUS-201514906502-A
CountryUS
Kind codeA1
Filing dateAug 18, 2015
Priority dateJan 29, 2015
Publication dateDec 29, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes an array substrate provided with a plurality of sub-pixels, and a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and independent of each other, and a plurality of touch lines connecting the self capacitive electrodes to the touch detection chip; the plurality of gate lines and the plurality of data lines are intersected with each other to define the plurality of sub-pixels; each of the sub-pixels includes a pixel electrode and is configured with a long side and a short side; and the touch lines are disposed along the direction of short sides of the sub-pixels.

First claim

Opening claim text (preview).

1 . An in-cell touch panel, comprising: an array substrate provided with a plurality of sub-pixels, a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and independent of each other, and a plurality of touch lines connecting the self capacitive electrodes to a touch detection chip, wherein the plurality of gate lines and the plurality of data lines are intersected with each other to define the plurality of sub-pixels; each of the sub-pixels is configured with a long side and a short side; and the touch lines are disposed along the direction of short sides of the sub-pixels. 2 . The in-cell touch panel according to claim 1 , wherein a pixel comprises sub-pixels, the sub-pixels of each pixel are connected with a data line and the plurality of gate lines respectively. 3 . The in-cell touch panel according to claim 1 , wherein the plurality of touch lines are disposed on the array substrate in a cycle of one or more pixels. 4 . The in-cell touch panel according to claim 1 , wherein the touch lines and the data lines are disposed on a same layer, insulated from each other, and are routed in a same direction. 5 . The in-cell touch panel according to claim 1 , wherein each of the sub-pixels comprises a pixel electrode, and pixel electrodes and the touch lines are disposed on a same layer at gaps between the two adjacent pixels. 6 . The in-cell touch panel according to claim 1 , further comprising a plurality of redundant metal lines which are insulated from each other and are disposed on a same layer as the touch lines are disposed; wherein each of the redundant metal lines is parallel to the touch lines and is connected in parallel with the self capacitive electrode which it overlaps. 7 . The in-cell touch panel according to claim 1 , wherein an insulating interlayer is provided between the self capacitive electrodes and the touch lines, and the self capacitive electrodes are electrically connected with the corresponding touch lines through via holes which run through the insulating interlayer. 8 . The in-cell touch panel according to claim 7 , wherein concave parts are provided in the insulating interlayer in the area in which the self capacitive electrodes overlaps other touch lines except the touch lines which are electrically connected with the self capacitive electrodes; a cross-section shape of the via holes is same as a cross-section shape of the concave parts, and the concave parts are uniformly distributed in the insulating interlayer. 9 . The in-cell touch panel according to claim 1 , wherein opposite side edges of two adjacent self capacitive electrodes are zigzag. 10 . The in-cell touch panel according to claim 9 , wherein the zigzag opposite side edges of the two adjacent self capacitive electrodes are configured as step-shaped structures, and the two step-shaped structures are of the same shape and match each other. 11 . The in-cell touch panel according to claim 9 , wherein the zigzag opposite side edges of the two adjacent self capacitive electrodes are configured as concave-convex shaped structures, and the two concave-convex shaped structures are of the same shape and match each other. 12 . The in-cell touch panel according to claim 1 , wherein the self capacitive electrodes constitute the common electrode layer which is on the array substrate. 13 . The in-cell touch panel according to claim 12 , wherein the common electrode layer is disposed between a pixel electrode layer of the array substrate and a base substrate of the array substrate, and an insulating layer is disposed between the pixel electrode layer and the common electrode layer. 14 . The in-cell touch panel according to claim 12 , wherein the pixel electrode layer is disposed between the common electrode layer and the base substrate of the array substrate, and an insulating layer is disposed between the pixel electrode layer and the common electrode layer. 15 . A display device, comprising the in-cell touch panel according to claim 1 . 16 . The in-cell touch panel according to claim 5 , wherein an insulating interlayer is provided between the self capacitive electrodes and the touch lines, and the self capacitive electrodes are electrically connected with the corresponding touch lines through via holes which run through the insulating interlayer. 17 . The in-cell touch panel according to claim 6 , wherein an insulating interlayer is provided between the self capacitive electrodes and the touch lines, and the self capacitive electrodes are electrically connected with the corresponding touch lines through via holes which run through the insulating interlayer. 18 . The in-cell touch panel according to claim 5 , wherein opposite side edges of two adjacent self capacitive electrodes are zigzag. 19 . The in-cell touch panel according to claim 6 , wherein opposite side edges of two adjacent self capacitive electrodes are zigzag. 20 . The in-cell touch panel according to claim 7 , wherein opposite side edges of two adjacent self capacitive electrodes are zigzag.

Assignees

Inventors

Classifications

  • Electrode mesh in capacitive digitiser: electrode for touch sensing is formed of a mesh of very fine, normally metallic, interconnected lines that are almost invisible to see. This provides a quite large but transparent electrode surface, without need for ITO or similar transparent conductive material · CPC title

  • G06F3/044Primary

    by capacitive means · CPC title

  • Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

  • G06F3/0412Primary

    Digitisers structurally integrated in a display · CPC title

  • Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate · CPC title

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What does patent US2016378254A1 cover?
An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes an array substrate provided with a plurality of sub-pixels, and a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and ind…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Beijing Boe Optoelectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F3/044. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Dec 29 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).