Gate dielectrics for complementary metal oxide semiconductors transistors and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12310101-B2
Application number	US-202017133208-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf 1-x Z x O 2 , where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes Hf 1-x Z x O 2 , where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.

First claim

What is claimed is:

1. A complementary metal oxide semiconductor (CMOS) structure, comprising:
a first transistor comprising:
a first gate dielectric layer above a first channel, the first gate dielectric layer comprising Hf 1-x Zr x O 2 , wherein the first gate dielectric layer has a thickness of at least 1.3 nm;
a first gate electrode coupled to the first channel through the first gate dielectric layer;
a gate dielectric layer comprising oxygen and one or more of aluminum, lanthanum or yttrium located between the first gate dielectric layer and the channel and having a thickness between 0.7 nm and 1 nm;
and
a first source region and a first drain region of a first conductivity type on opposite sides of the first gate electrode; and

a second transistor comprising:
a second gate dielectric layer above a second channel, the second gate dielectric layer comprising Hf 1-x Zr x O 2 , wherein x for the second gate dielectric layer is greater than x for the first gate dielectric layer;
a second gate electrode coupled to the second channel through the second gate dielectric layer; and
a second source region and a second drain region of a second, complementary, conductivity type on opposite sides of the second gate electrode.

2. The CMOS structure of claim 1 , wherein x for the first gate dielectric layer is less than 0.5.

3. The CMOS structure of claim 1 , wherein the first gate dielectric layer comprises La, Y or Sr at a concentration of less than 5 atomic percent.

4. The CMOS structure of claim 1 , wherein the second gate dielectric layer comprises Al or Nb at a concentration of less than 5 atomic percent.

5. The CMOS structure of claim 1 , wherein the first dielectric layer is a first thickness and the second dielectric layer is a second thickness, and wherein the first thickness is greater than the second thickness by at least 0.2 nm.

6. The CMOS structure of claim 1 , wherein the first gate dielectric layer comprises a monoclinic crystal structure and the second gate dielectric layer comprises an orthorhombic or a tetragonal crystal structure.

7. The CMOS structure of claim 1 , wherein the first gate electrode comprises hafnium, zirconium, titanium, tantalum, aluminum, or carbon, and wherein the second gate electrode comprises ruthenium, palladium, platinum, cobalt, nickel or titanium nitride.

8. The CMOS structure of claim 1 , wherein the first transistor further comprises a third gate dielectric layer comprising silicon and oxygen between the first gate dielectric layer and the first channel and the second transistor further comprises a fourth gate dielectric layer comprising silicon and oxygen between the second gate dielectric layer and the second channel, wherein the third gate dielectric layer has a thickness that is greater than a thickness of the fourth gate dielectric layer by at least 0.1 nm.

9. The CMOS structure of claim 1 , wherein the first transistor further comprises a first dielectric spacer adjacent to the first gate electrode, and wherein the first gate dielectric layer is adjacent to sidewalls of the first dielectric spacer, the second transistor further comprises a second dielectric spacer adjacent to the second gate electrode, and wherein the second gate dielectric layer is adjacent to sidewalls of the second dielectric spacer.

10. A complementary metal oxide semiconductor (CMOS) structure, comprising:
an NMOS transistor, comprising:
a first gate dielectric layer above a first channel, the first gate dielectric layer comprising Hf, Zr, and O;
a first gate electrode coupled to the first channel through the first gate dielectric layer; and
a first source region and a first drain region on opposite sides of the first gate electrode; and

a PMOS transistor, comprising:
a second gate dielectric layer above a second channel, the second gate dielectric layer comprising Hf, Zr, and O, and wherein second gate dielectric layer has greater Zr content than the first gate dielectric layer;
a second gate electrode coupled to the second channel through the second gate dielectric layer; and
a second source region and a second drain region on opposite sides of the second gate electrode.

11. The CMOS structure of claim 10 , wherein the second gate dielectric layer comprises Hf 1-x and Zr x , and wherein x is greater than 0.5.

12. The CMOS structure of claim 11 , wherein the first gate dielectric layer comprises Hf 1-x and Zr x , and wherein x for the first gate dielectric layer is less than 0.5.

13. The CMOS structure of claim 12 , wherein the first gate dielectric layer comprises La, Y or Sr at a concentration of less than 5 atomic percent, and wherein the second gate dielectric layer comprises Al or Nb at a concentration of less than 5 atomic percent.

Assignees

• Intel Corp

Inventors

• Penumatcha Ashish Verma
• Sung Seung Hoon
• Kavalieros Jack
• Avci Uygar
• Tronic Tristan
• Shivaraman Shriram
• Merrill Devin
• Brown-Heft Tobias
• Maxey Kirby
• Metz Matthew
• Young Ian

Classifications

• H10N50/10

  Magnetoresistive devices · CPC title

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10N70/8833

  Binary metal oxides, e.g. TaOx · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title