Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12310017-B2
Application number	US-202117466200-A
Country	US
Kind code	B2
Filing date	Sep 3, 2021
Priority date	Sep 15, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

According to one embodiment, a semiconductor device includes: a stacked body including an insulating layer, and a conductive layer containing molybdenum; an aluminum oxide layer provided between the insulating layer and the conductive layer; and a protective layer in contact with the aluminum oxide layer, containing one of carbon, nitrogen, or sulfur bonded to aluminum in the aluminum oxide layer, and also in contact with the conductive layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a stacked body including:
an insulating layer;
a conductive layer containing molybdenum;
an aluminum oxide layer provided between the insulating layer and the conductive layer; and
a protective layer in contact with the aluminum oxide layer, containing sulfur bonded to aluminum in the aluminum oxide layer, and also in contact with the conductive layer;

wherein the aluminum oxide layer is configured to prevent tunneling charges from the conductive layer.

2. The semiconductor device according to claim 1 , wherein the stacked body further includes an insulator provided adjacent the insulating layer and the conductive layer, and in contact with a portion of the insulating layer, a portion of the aluminum oxide layer, a portion of the protective layer, and a portion of the conductive layer.

3. The semiconductor device according to claim 2 , wherein the stacked body further includes:
a semiconductor layer provided adjacent the insulating layer and the conductive layer, and extending in a stacking direction of the stacked body;
a tunnel insulating layer provided between the conductive layer and the semiconductor layer;
a charge trapping layer provided between the tunnel insulating layer and the conductive layer; and
a cover insulating layer provided between the charge trapping layer and the conductive layer.

4. The semiconductor device according to claim 3 , wherein a memory cell includes respective portions of the conductive layer, the semiconductor layer, the tunnel insulating layer, the charge trapping layer, the cover insulating layer, the insulating layer, and the aluminum oxide layer, and
the memory cell corresponds to the conductive layer among a plurality of conductive layers alternately stacked with a plurality of insulating layers.

5. The semiconductor device according to claim 4 , wherein the memory cell includes a control gate that controls writing or erasing for the memory cell, and the plurality of conductive layers are connected to a plurality of control gates, respectively.

6. The semiconductor device according to claim 1 , wherein the conductive layer contains impurities of chlorine.

7. The semiconductor device according to claim 2 , wherein the aluminum oxide layer wraps around a top surface, a bottom surface, and a first sidewall of the conductive layer, with a second sidewall of the conductive layer in contact with the insulator.

8. The semiconductor device according to claim 2 , wherein the protective layer wraps around a top surface, a bottom surface, and a first sidewall of the conductive layer, with a second sidewall of the conductive layer in contact with the insulator.

Assignees

• Kioxia Corp

Inventors

• Kitamura Masayuki
• Hirohashi Takuya
• Kinoshita Shigeru
• Toyota Hiroshi

Classifications

• H10B43/10

  characterised by the top-view layout · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title