Solid-state imaging element

Patent metadata

Field	Value
Publication number	US-12309518-B2
Application number	US-202118040947-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Aug 20, 2020
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Provided is a solid-state imaging element provided with a comparator for each column, the solid-state imaging element improving the image quality of image data. The solid-state imaging element includes a first comparison element and a transistor. An input voltage related to the voltage of a vertical signal line is input to a source of the first comparison element, and the first comparison element outputs a drain voltage corresponding to the gate-source voltage from a drain. A signal corresponding to the voltage of the vertical signal line is input to a gate of the transistor, and a source of the transistor is connected to the drain of the first comparison element.

First claim

The invention claimed is:

1. A solid-state imaging element, comprising:
a first comparison element that has a source to which an input voltage related to a voltage of a vertical signal line is input, the first comparison element outputting a drain voltage corresponding to a gate-source voltage from a drain; and
a transistor that has a gate to which a signal corresponding to the voltage of the vertical signal line is input, and a source connected to the drain of the first comparison element.

2. The solid-state imaging element according to claim 1 , wherein
the source of the first comparison element is connected to the vertical signal line,
the first comparison element has a gate to which a predetermined reference voltage is input,
the first comparison element transitions from an off state to an on state in a case where the input voltage and the predetermined reference voltage substantially coincide with each other, and
the transistor includes a first clamp transistor that fixes the drain voltage in the off state to a clamp voltage corresponding to the input voltage.

3. The solid-state imaging element according to claim 2 , further comprising a clamp voltage controller that supplies the signal to a gate of the first clamp transistor, wherein
the first clamp transistor is inserted between the drain and the source of the first comparison element.

4. The solid-state imaging element according to claim 3 , further comprising a second clamp transistor connected in parallel to the first clamp transistor, wherein
the second clamp transistor has a gate to which a fixed voltage is applied.

5. The solid-state imaging element according to claim 3 , wherein
the clamp voltage controller includes a capacitor inserted between the vertical signal line and the gate of the first clamp transistor.

6. The solid-state imaging element according to claim 3 , wherein
the clamp voltage controller divides a voltage between the voltage of the vertical signal line and a predetermined reference potential and supplies the divided voltage to the gate of the first clamp transistor.

7. The solid-state imaging element according to claim 6 , further comprising an initialization circuit that samples the voltage of the vertical signal line, holds the sampled voltage as a held voltage, and initializes a gate voltage of the first clamp transistor on a basis of the held voltage.

8. The solid-state imaging element according to claim 7 , wherein
the initialization circuit samples and holds a pixel signal of a pixel circuit.

9. The solid-state imaging element according to claim 7 , wherein
the initialization circuit samples and holds a pixel signal of a light-shielded pixel that is shielded from light.

10. The solid-state imaging element according to claim 7 , wherein
the initialization circuit samples and holds a pixel signal of a dummy pixel.

11. The solid-state imaging element according to claim 7 , wherein
a driver samples and holds a pixel signal of a dummy pixel that is shielded from light.

12. The solid-state imaging element according to claim 6 , further comprising a counter that counts a count value during a period until the drain voltage is inverted.

13. The solid-state imaging element according to claim 12 , further comprising:
a correction coefficient calculation unit that calculates a correction coefficient for correcting a conversion gain that is a ratio between the input voltage and the count value; and
a correction unit that corrects a digital signal indicating the count value on a basis of the correction coefficient.

14. The solid-state imaging element according to claim 12 , further comprising:
a controller that calculates a correction coefficient for correcting a conversion gain that is a ratio between the input voltage and the count value, and controls the predetermined reference voltage on a basis of the correction coefficient.

15. The solid-state imaging element according to claim 1 , wherein
the transistor includes an auto-zero switch that short-circuits a gate and the drain of the first comparison element in accordance with the signal.

16. The solid-state imaging element according to claim 15 , wherein
the source of the first comparison element is connected to the vertical signal line, and
a predetermined reference voltage is input to the gate of the first comparison element.

17. The solid-state imaging element according to claim 15 , further comprising a driver that generates a predetermined control signal as the signal on a basis of the voltage of the vertical signal line.

18. The solid-state imaging element according to claim 17 , wherein
the driver supplies one of two values as the predetermined control signal.

19. The solid-state imaging element according to claim 17 , wherein
the driver samples and holds a pixel signal of a pixel circuit, and generates the predetermined control signal on a basis of the held pixel signal.

20. The solid-state imaging element according to claim 17 , wherein
the driver samples and holds a pixel signal of a light-shielded pixel shielded from light, and generates the predetermined control signal on a basis of the held pixel signal.

21. The solid-state imaging element according to claim 17 , wherein
the driver generates the predetermined control signal on a basis of a pixel signal of a dummy pixel.

22. The solid-state imaging element according to claim 21 , wherein
the driver generates the predetermined control signal on a basis of the pixel signal of the dummy pixel that is shielded from light.

23. The solid-state imaging element according to claim 17 , wherein
the first comparison element is disposed in a column amplifier that amplifies the voltage of the vertical signal line and supplies the amplified voltage to an analog-to-digital converter.

24. The solid-state imaging element according to claim 17 , further comprising
a second comparison element that has a gate to which the voltage of the vertical signal line is input, a drain connected to a power supply voltage, and a source connected to the source of the first comparison element.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Awatani Yoshio
• Moyade Pawankumar Pradeepkumar

Classifications

• H04N25/75

  Circuitry for providing, modifying or processing image signals from the pixel array · CPC title

• H04N25/772

  comprising A/D, V/T, V/F, I/T or I/F converters · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/703

  SSIS architectures incorporating pixels for producing signals other than image signals · CPC title

• H04N25/78 Primary

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title