Photoelectric conversion apparatus and photoelectric conversion system

US2016295142A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016295142-A1
Application numberUS-201615082937-A
CountryUS
Kind codeA1
Filing dateMar 28, 2016
Priority dateMar 30, 2015
Publication dateOct 6, 2016
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In a photoelectric conversion apparatus, a pixel transistor and a differential transistor form a differential pair. A clamp circuit clamps a gate voltage of the differential transistor. An output circuit performs a first operation in which a voltage based on the voltage at the gate of a pixel transistor is output to the gate of the differential transistor. The output circuit also performs a second operation in which in response to receiving a current from the differential transistor, a signal based on a result of a comparison between the gate voltage of the pixel transistor and the gate voltage of the differential transistor is output to the output node. In the second operation, a control unit in the output circuit controls a change in the drain voltage of the differential transistor to be smaller than a change in the voltage at the output node.

First claim

Opening claim text (preview).

What is claimed is: 1 . A photoelectric conversion apparatus comprising: a photoelectric conversion element; a differential pair including a first transistor configured to receive a signal based on an electric charge generated in the photoelectric conversion element and a second transistor configured to receive a reference signal; a clamp circuit configured to clamp a voltage at a gate of the second transistor; and an output circuit configured to perform. a first operation to output a voltage based on a voltage at a gate of the first transistor to the gate of the second transistor, and a second operation to receive a current from the second transistor, and to output a signal based on a result of a comparison between the voltage at the gate of the first transistor and a voltage at the gate of the second transistor to an output node, wherein the output circuit includes a control unit configured to control, in the second operation, an amount of change in a voltage at a drain of the second transistor so as to be smaller than an amount of change in a voltage at the output node. 2 . The photoelectric conversion apparatus according to claim 1 , wherein the control unit includes a current mirror circuit including a third transistor electrically connected to the drain of the second transistor and a fourth transistor having a gate connected to a gate of the third transistor, in the first operation, the current mirror circuit mirrors a current of the fourth transistor to the third transistor, and in the second operation, the current mirror circuit mirrors a current of the third transistor to the fourth transistor. 3 . The photoelectric conversion apparatus according to claim 2 , wherein the control unit includes a first switch element that connects the gate and a drain of the fourth transistor, in response to turning-on of the first switch element, the current mirror circuit mirrors the current of the fourth transistor to the third transistor, and in response to turning-off of the first switch element, the current mirror circuit mirrors the current of the third transistor to the fourth transistor. 4 . The photoelectric conversion apparatus according to claim 3 , wherein the control unit includes a capacitor element having a first terminal electrically connected to a drain of the third transistor and a second terminal electrically connected to the gate of the third transistor. 5 . The photoelectric conversion apparatus according to claim 4 , wherein the first terminal of the capacitor element is electrically connected to the drain of the third transistor via a common gate circuit. 6 . The photoelectric conversion apparatus according to claim 4 , wherein a capacitance of the capacitor element is greater than a capacitance of a coupling capacitor between two terminals of the first switch element in an off-state. 7 . The photoelectric conversion apparatus according to claim 3 , wherein the control unit includes a second switch element that electrically connects a drain and the gate of the third transistor. 8 . The photoelectric conversion apparatus according to claim 7 , wherein the second switch element is electrically connected to the drain of the third transistor via a common gate circuit. 9 . The photoelectric conversion apparatus according to claim 7 , wherein the first switch element and the second switch element operate in a complementary manner. 10 . The photoelectric conversion apparatus according to claim 3 , wherein the clamp circuit includes a clamp switch element connected to the gate of the second transistor, and the clamp switch element and the first switch element operate in a synchronous phase. 11 . The photoelectric conversion apparatus according to claim 2 , wherein in the first operation, the current mirror circuit operates as a current source that supplies a current provided by the third transistor to the second transistor, and in the second operation, the current mirror circuit operates as a current detection circuit that mirrors, into the fourth transistor, a current input to the third transistor from the second transistor. 12 . The photoelectric conversion apparatus according to claim 2 , wherein the control unit includes a load transistor electrically connected to the drain of the second transistor, the second transistor and the third transistor are connected so as to receive a current from the load transistor complementarily, in the first operation, the load transistor operates as a current source that supplies a current to the second transistor, and in the second operation, the current mirror circuit operates as a current detection circuit that mirrors, into the fourth transistor, a current input to the third transistor from the load transistor. 13 . The photoelectric conversion apparatus according to claim 12 , wherein the control unit includes a common gate circuit disposed in an electric path between the load transistor and the third transistor. 14 . The photoelectric conversion apparatus according to claim 1 , wherein the control unit includes a first current mirror circuit electrically connected to a drain of the first transistor and configured to output a current to a first mirror output node by mirroring a current from the first transistor, and a second current mirror circuit electrically connected to the drain of the second transistor and configured to output a current to a second mirror output node by mirroring a current from the second transistor, and the clamp circuit includes a clamp switch element connecting the gate of the second transistor and the output node of the output circuit. 15 . The photoelectric conversion apparatus according to claim 14 , wherein the control unit includes a third current mirror circuit configured to mirror a current from one of the first mirror output node and the second mirror output node, and to output a mirrored current to another one of the first mirror output node and the second mirror output node. 16 . The photoelectric conversion apparatus according to claim 1 , wherein the clamp circuit includes a clamp switch element connected to the gate of the second transistor, and a clamp capacitor element having a first terminal connected to the gate of the second transistor and a second terminal configured to receive the reference signal. 17 . The photoelectric conversion apparatus according to claim 16 , wherein the clamp switch element connects the gate and the drain of the second transistor. 18 . The photoelectric conversion apparatus according to claim 16 , wherein the clamp switch element electrically connects the gate and the drain of the second transistor via a common gate circuit. 19 . The photoelectric conversion apparatus according to claim. 1 , wherein the control unit controls an amount of change in the voltage at the drain of the second transistor that occurs in response to an inversion of a relationship between the voltage at the gate of the first transistor and the voltage at the gate of the second transistor so as to be smaller than an amount of change in the voltage at the output node that occurs in response to the inversion. 20 . The photoelectric conversion apparatus according to claim 1 , comprising a reference current source connected to the output node and configured to output a reference current. 21 . The photoelectric conversion apparatus according to claim 1 , comprising an inverter circuit connected to the output node. 22

Assignees

Inventors

Classifications

  • H04N25/77Primary

    Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

  • Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels · CPC title

  • comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

  • H04N25/76Primary

    Addressed sensors, e.g. MOS or CMOS sensors · CPC title

  • SSIS architectures; Circuits associated therewith · CPC title

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What does patent US2016295142A1 cover?
In a photoelectric conversion apparatus, a pixel transistor and a differential transistor form a differential pair. A clamp circuit clamps a gate voltage of the differential transistor. An output circuit performs a first operation in which a voltage based on the voltage at the gate of a pixel transistor is output to the gate of the differential transistor. The output circuit also performs a sec…
Who is the assignee on this patent?
Canon Kk
What technology area does this patent fall under?
Primary CPC classification H04N25/77. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 06 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).