Dual loop charge pump for enhanced reliability and power consumption

Patent metadata

Field	Value
Publication number	US-12308847-B2
Application number	US-202318338492-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Jun 21, 2023
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

Embodiments of the present disclosure provide an enhanced phase-locked loop (PLL) circuit and an enhanced charge pump circuit used for various applications, including high-speed data clock generation for complex integrated circuit (IC) designs. The disclosed PLL circuit and charge pump circuit enable significant power and supply current reduction, improved circuit reliability; reduced self-heating and electro-migration risk, and enable use of lower power operational amplifiers with the operational amplifiers driving high impedance nodes.

First claim

What is claimed is:

1. A charge pump circuit comprising:
an H-bridge circuit; an input of the H-bridge circuit coupled to a phase frequency detector to receive respective increment and decrement control signals from the phase frequency detector;
an output of the H-bridge circuit coupled to a loop filter to control current flow to and from the loop filter based on the respective increment and decrement control signals;
a first loop control comprising a sense operational amplifier coupled to the H-bridge circuit, wherein the sense operational amplifier provides an output configured to drive a pair of H-bridge footer transistors providing a charge pump current to match respective voltages at a first charge pump node and a second charge pump node; and
a second loop control coupled to the H-bridge circuit configured to drive an H-bridge header transistor to adjust a common mode voltage at the second charge pump node and a third charge pump node, the second charge pump node and the third charge pump node coupled to the loop filter.

2. The charge pump circuit of claim 1 , wherein the sense operational amplifier having a first input and a second input respectively coupled to the first charge pump node and the second charge pump node.

3. The charge pump circuit of claim 1 , wherein the second loop control comprises a common mode (CM) operational amplifier, the CM operational amplifier having a first input coupled to the first charge pump node and a fourth charge pump node and a second input coupled to the common mode voltage.

4. The charge pump circuit of claim 1 , wherein an output of a common mode (CM) operational amplifier provides an output configured to drive the H-bridge header transistor to maintain the common mode voltage at the second charge pump node and the third charge pump node.

5. The charge pump circuit of claim 1 , the output of the H-bridge circuit coupled to the loop filter controls current flow from the loop filter to discharge at least one capacitor of the loop filter based on a high decrement control signal from the phase frequency detector.

6. The charge pump circuit of claim 1 , wherein the output of the H-bridge circuit coupled to the loop filter controls current flow to the loop filter to charge at least one capacitor of the loop filter based on a high increment control signal from the phase frequency detector.

7. The charge pump circuit of claim 1 , wherein the H-bridge circuit comprises a plurality of switching transistors coupled between a current reference header transistor and a first transistor of the pair of H-bridge footer transistors.

8. The charge pump circuit of claim 1 , wherein the H-bridge circuit comprises a plurality of switching transistors coupled between the H-bridge header transistor and a second transistor of the pair of H-bridge footer transistors.

9. The charge pump circuit of claim 1 , wherein the H-bridge circuit comprises a gate enable control logic circuit providing gate drive inputs to a plurality switching transistors of the H-bridge circuit, the gate drive inputs based on the respective increment and decrement control signals from the phase frequency detector.

10. The charge pump circuit of claim 1 , wherein the H-bridge circuit comprises a plurality of identical charge pump slices cascaded together, the first charge pump node, the second charge pump node, and the third charge pump node connected to each of the charge pump slices.

11. The charge pump circuit of claim 1 , wherein the pair of H-bridge footer transistors and the H-bridge header transistor comprise MOS (metal-oxide semiconductor) FinFETs (Fin Field Effect Transistors).

12. The charge pump circuit of claim 1 , wherein the second loop control comprises a common mode (CM) operational amplifier and wherein the sense operational amplifier and the CM operational amplifier comprise low power operational amplifiers configured to drive a high impedance charge pump node.

13. The charge pump circuit of claim 1 , wherein the first loop control comprises a single current reference circuit.

14. A phase-locked loop (PLL) circuit comprising:
a reference clock signal;
a voltage controlled oscillator (VCO) circuit having a VCO output frequency controlled by a input control voltage;
a feedback divider coupled to the VCO circuit dividing the VCO output frequency to provide a feedback clock signal;
a phase frequency detector coupled to the feedback divider comparing the reference clock signal and the feedback clock signal, the phase frequency detector generating respective increment and decrement control signals based on comparing the reference clock signal and the feedback clock signal;
a charge pump circuit comprising an input coupled to the phase frequency detector to receive the respective increment and decrement control signals and an output coupled to a loop filter to control current flow to charge, or to discharge at least one capacitor of the loop filter based on the respective increment and decrement control signals;
the charge pump circuit comprising a first loop control comprising a sense operational amplifier that provides an output configured to drive a pair of charge pump footer transistors providing a charge pump current to match respective voltages at a first charge pump node and a second charge pump node; and a second loop control configured to drive a charge pump header transistor to adjust a common mode voltage at the second charge pump node and a third charge pump node, the second charge pump node and the third charge pump node coupled to the loop filter; and
the loop filter providing the input control voltage to the VCO circuit.

15. The PLL circuit of claim 14 , wherein the charge pump footer transistors and the charge pump header transistor comprise MOS (metal-oxide semiconductor) FinFETs (Fin Field Effect Transistors).

16. The PLL circuit of claim 14 , the sense operational amplifier having a first input and a second input respectively coupled to the first charge pump node and the second charge pump node.

17. The PLL circuit of claim 14 , wherein the second loop control comprises a common mode (CM) operational amplifier, the CM operational amplifier having a first input coupled to the first charge pump node and a fourth charge pump node, and a second input coupled to the common mode voltage.

18. The PLL circuit of claim 17 , wherein the CM operational amplifier provides an output configured to drive the charge pump header transistor to maintain the common mode voltage at the second charge pump node and the third charge pump node.

Assignees

• IBM

Inventors

• Strom James
• Borkenhagen John
• Wu Ann Chen
• Bindu Rashmi

Classifications

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/0896

  the current generators being controlled by differential up-down pulses · CPC title

• H03L7/0895 Primary

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H03L7/0893 Primary

  the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop · CPC title